将std_logic与'X'进行比较时如何获得模拟警告? [英] How to get simulation warning when comparing std_logic with 'X'?

问题描述

为了在模拟中捕捉到更多的bug，得到警告是一个优势如果在 = 比较中使用 std_logic 和 'X'.

In order to catch more bugs in simulation, it is an advantage to get a warning if std_logic with 'X' is used in = compare.

当使用 ieee.std_logic_1164 包时，std_logic 比较函数= 不会对任一操作数中的 'X' 发出警告.所以'if'分支在当 sl_i 为 '1' 时采用下面的代码，但采用 else 分支当 sl_i 为 '0'、'X' 等时:

When using the ieee.std_logic_1164 package, the std_logic compare function = does not warn about 'X' in either of the operands. So the ´if´ branch in the code below is taken when sl_i is '1', but the else branch is taken when sl_i is either of '0', 'X', etc.:

if sl_i = '1' then
  sl_o <= '1';
else  -- sl_i in "UX0ZWLH-"
  sl_o <= '0';
end if;

因此例如 'X' 或 'U'，由于使用了一些未知或未初始化的值，在模拟过程中被默默忽略.但是，如果发出警告，它将提高在模拟中发现错误的可能性，例如ieee.numeric_std 包警告元值('X' 等)与=.

So for example an 'X' or 'U', due to use of some unknown or uninitialized value, is silently ignored during simulation. However, if a warning was given, it would improve the possibility of finding bugs in simulation, like when the ieee.numeric_std package warns about metavalue ('X' etc.) in compare with =.

?是否有任何标准的 VHDL 方法来获取 std_logic 中元值的警告与 = 比较?

? Is there any standard VHDL way to get warning for metavalues in std_logic at compare with = ?

一种可能性，是制作一个包，其中 std_logic 的隐式 = 是重新定义，然后将此包与 .all 一起使用，以便替换 =.这样的包可能看起来像:

One possibility, is to make a package where the implicit = for std_logic is redefined, and then use this package with .all so the = is replaced. Such package with may look like:

library ieee;
use ieee.std_logic_1164.std_logic;

package std_logic_warning is
  function "="(l, r : std_logic) return boolean;
end package;

library ieee;
use ieee.std_logic_1164.is_x;
use ieee.std_logic_1164;  -- For access to "=" using std_logic_1164."="

package body std_logic_warning is

  function "="(l, r : std_logic) return boolean is
  begin
    assert not (is_x(l) or is_x(r))
      report "std_logic_warning.""="": metavalue detected"
      severity WARNING;
    return std_logic_1164."="(l, r);
  end function;

end package body;

?这样的重新定义是否符合 VHDL 标准，是否可行?使用一般工具?

? Will such a redefine be VHDL standard compliant, and is it likely to work with the tools in general ?

正如 Jim Lewis 在参考 ISAC 时指出的那样IR2058 的想法使用时覆盖隐式 = 可能通常不适用于工具VHDL-2003.VHDL-2008 应该可以解决这个问题.

As Jim Lewis points out with reference to ISAC IR2058 the idea of overriding the implicit = may not work in general for tool when using VHDL-2003. VHDL-2008 should fix this.

请注意，以上问题和建议已根据 David Koontz 进行编辑以前的评论.

Note that above question and suggestion has been edited based on David Koontz previous comments.

推荐答案

根据您使用的语言版本，您可能会遇到可移植性问题.我建议您使用 VHDL-2008 来避免它们，它消除了许多问题.

Depending on which language revision you are using, you may experience portability problems. I suggest you avoid them by using VHDL-2008, which removes a number of issues.

在 VHDL-2008 之前，某些工具不允许显式运算符重载隐式运算符.在 VHDL-2008 之前，工具以不同方式解释对ieee.std_logic_1164.std_logic"的引用.有关讨论，请参阅 ISAC IR2058:http://www.eda.org/isac/IRs-VHDL-2002/IR2058.txt.即使实现了 IR2058，我的解释是 is_x 不会包含在您对 std_logic 的引用中，因为只包含重载的运算符而不是所有函数 - 因此，如果可行，它可能无法在工具之间移植.

Prior to VHDL-2008, some tools did not allow explicit operators to overload implicit operators. Prior to VHDL-2008, tools interpreted the reference to "ieee.std_logic_1164.std_logic" differently. See ISAC IR2058 for a discussion: http://www.eda.org/isac/IRs-VHDL-2002/IR2058.txt. Even with the implementation of IR2058, my interpretation is that is_x will not be included in your reference to std_logic as only overloaded operators are included and not all functions - so if that works it is probably not portable between tools.

因此，我将使用 VHDL-2008 和以下代码.我将 ieee.std_logic_1164."=" 的引用替换为对 ieee.numeric_std.std_match 的引用，因为我不清楚一旦显式运算符可见以替换它，您是否仍然可以引用隐式运算符 - 即使它是合法，我希望这是一个可能会破坏工具的边缘案例(确保报告错误).使用 std_match 还具有正确处理L"或H"的好处.

Hence, I would use VHDL-2008 and the following code. I replaced the reference to ieee.std_logic_1164."=" with one to ieee.numeric_std.std_match, as it is not clear to me if you can still reference an implicit operator once an explicit operator is visible to replace it - even if it is legal, I would expect this to be a fringe case that may break tools (make sure to report the bugs). Use of std_match also has the benefit of correctly handling an 'L' or 'H'.

library ieee;
use ieee.std_logic_1164.all;

package std_logic_warning is
  function "="(l, r : std_logic) return boolean;
end package;

package body std_logic_warning is

  function "="(l, r : std_logic) return boolean is
  begin
    assert not (is_x(l) or is_x(r))
      report "std_logic_warning.""="": metavalue detected"
      severity WARNING;
    return ieee.numeric_std.std_match(l, r);
  end function;

end package body;

如果您不喜欢 std_match 的行为，您可以使用 std_match 作为模板来创建功能，但是，我不建议这样做，因为综合工具可能不喜欢它.

If you don't like the behavior of std_match, you can use std_match as a template to create the functionality, however, I don't recommend this as synthesis tools may not like it.

虽然您可以使用修改后的="作为反建议，但有两个 X 来源，来自其他设计的外部和来自未初始化寄存器的内部.我不担心未初始化的寄存器，因为我对重置很严格.因此，在核心级别，我可能(取决于我对其他人或测试平台的信心)直接在核心输入上使用 assert 语句.

While you could use the modified "=", as a counter suggestion, there are two sources of X, external from other designs and internal from uninitialized registers. I don't worry about uninitialized registers as I am rigorous about my resets. Hence, at the core level, I may (depending on my confidence of others or the testbench), use the assert statement directly on core inputs.

assert not is_x(core_input_1) 
  report "meta value detected on core_input_1" severity ERROR ; 

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