仅使用 std_logic_vector 包将 std_logic_vector 与常量进行比较 [英] Compare std_logic_vector to a constant using std_logic_vector package ONLY

问题描述

我只在我的 VHDL 文件中使用以下包:

I use the following package only in my VHDL file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

在代码中，我将 std_logic_vector 信号:A 与一个常量值进行比较，例如

In the code, I compare a std_logic_vector signal : A with a constant value, e.g

...if A<="00001011" then

但代码已被 Xilinx ISE 正确检查.我的理解是 STD_LOGIC_1164 包不包含作为操作数 std_logic_vector 的不等式的实现，那么为什么上述代码语句被接受，上述比较将 A 视为有符号数还是无符号数?

yet the code was checked correctly by Xilinx ISE. My understanding is that STD_LOGIC_1164 package does not include an implementation of inequalities having as an operand std_logic_vector so why the above code statement was accepted and will the above comparison treat A as signed or unsigned number?

推荐答案

-- 复制我对 comp.lang.vhdl 的回复.抱歉，有些重复，但有些没有.

-- Copying my comp.lang.vhdl reply to this post. Sorry some duplicates, but some does not.

所有枚举类型和枚举类型数组都隐式定义了常规排序关系运算符(>、>=、<、<=).不幸的是，它没有按数字顺序排列，因此结果可能与预期不符.相反，它是按字典排序的.

All enumerated types and arrays of enumerated types implicitly define the regular ordering relational operators (>, >=, <, <=). Unfortunately it is not numerically ordered, so the results may not be as expected. Instead it is dictionary ordered.

首先要看元素类型，即std_logic，其基类型是std_ulogic.对于枚举类型，例如 std_ulogic，左值小于右值，因此，对于 std_ulogic(和 std_logic):'U' <'X' <'0' <'1' <'Z' <'W' <'L' <'H' <'-'

First you have to look at the element type, which is std_logic whose base type is std_ulogic. For an enumerated type, such as std_ulogic, left values are less than right values, hence, for std_ulogic (and std_logic): 'U' < 'X' < '0' < '1' < 'Z' < 'W' < 'L' < 'H' < '-'

对于元素基类型为 std_ulogic(例如 std_logic_vector 或 std_ulogic_vector)且值仅为 0 或 1 的等长数组，一切正常:1010">0101"

For equal length arrays whose element base type is std_ulogic (such as std_logic_vector or std_ulogic_vector) whose values are only 0 or 1, things work out fine: "1010" > "0101"

注意字典比较总是先比较左边的元素.因此，对于字符串，以 'S' 开头的内容总是小于以 'T' 开头的内容，与长度无关.这对于将字符串排序到字典中非常有用，并且是唯一实用的默认值 - 如果我们要提供这样的东西.

Note that dictionary comparisons always compare the left element first. Hence, for string, something that starts with 'S' is always less than something that starts with 'T' independent of length. This is great for sorting strings into a dictionary and is the only practical default - if we are going to provide such as thing.

OTOH，如果您认为事物是数字，这不是很好.例如，如果数组的长度不相等，则以下情况为真，因为左侧参数的前导1"> 右侧参数的前导0".
100">0111"

OTOH, this is not so great if you are thinking things are numeric. For example, if the arrays are not equal length, then the following is true because the leading '1'on the left parameter is > the leading '0' of the right parameter.
"100" > "0111"

因此，仅使用use ieee.std_logic_1164.all"，您就有可能接触到错误的编码实践，错误地将 std_logic_vector 视为数字(例如无符号).

Hence, with only "use ieee.std_logic_1164.all", you have potential exposure to bad coding practices that mistakenly think of std_logic_vector as numeric (such as unsigned).

许多人会争辩说，永远不要将 std_logic_vector 用于数学，而 ">" 是数学.我基本同意.

Many will argue, never use std_logic_vector for math and ">" is math. I generally agree.

那我该怎么办?我如何保护我的设计和设计团队免受此影响.首先，您必须决定一项政策以及如何实施它.

So what do I do? How do I protect my design and design team from this. First you have to decide a policy and how to implement it.

1) 禁止将常规排序关系运算符(>、>=、<、<=)与 std_logic_vector 一起使用，并使用 lint 工具强制执行.但是，这意味着您必须购买并要求使用 lint 工具.

1) Forbid use of regular ordering relational operators (>, >=, <, <=) with std_logic_vector and enforce it with a lint tool. However this means you have to buy and require the use of a lint tool.

2) 禁止在 std_logic_vector 中使用常规排序关系运算符(>、>=、<、<=)，并通过使用以下两个包引用来强制执行.请注意，这会通过为每个运算符引用两个定义而产生错误，因此，当使用该表达式时，该表达式会变得不明确.请注意，这可能会有问题，因为 numeric_std_unsigned 是在 1076-2008 年引入的，并且您的综合工具可能尚不支持它.
图书馆 IEEE ;使用 ieee.numeric_std_unsigned.all ；使用 ieee.std_logic_unsigned.all ;

2) Forbid use of regular ordering relational operators (>, >=, <, <=) with std_logic_vector and enforce it by using the both of the following package references. Note that this generates errors by referencing two definitions for each of the operators, and hence, when used the expression becomes ambiguous. Note this may be problematic since numeric_std_unsigned was introduced in 1076-2008 and it may not yet be supported by your synthesis tools.
library ieee ; use ieee.numeric_std_unsigned.all ; use ieee.std_logic_unsigned.all ;

3) 放宽一些规则.我们最关心的是设计的正确性.允许将 std_logic_vector 解释为无符号值并引用 numeric_std_unsigned (首选，但它是 VHDL-2008 并且可能尚未由您的综合工具实现 - 但如果不确定提交错误报告)或 std_logic_unsigned (不是首选 - 这是一个旧的共享软件包，它不是 IEEE 标准，可能不属于 IEEE 库 - OTOH，它得到了很好的支持，并且它与其他包一起玩得很好 - 例如 numeric_std).

3) Relax the rules some. Our biggest concern is design correctness. Allow std_logic_vector to be interpreted as an unsigned value and either reference numeric_std_unsigned (preferred, but it is VHDL-2008 and may not be implemented by your synthesis tool yet - but if it is not be sure to submit a bug report) or std_logic_unsigned (not preferred - this is an old shareware package that is not an IEEE standard and perhaps does not belong in the IEEE library - OTOH, it is well supported and it plays nice with other packages - such as numeric_std).

这样做的好处是它还允许包含整数的比较:如果 A <= 11 那么

The nice result of this is that it also allows comparisons that include integers: if A <= 11 then

注意，有人建议在 numeric_std_unsigned/std_logic_unsigned 中重载>"和朋友是非法的.这是 VHDL-2008 之前对 1076 的非常保守的解释.在 VHDL-2008 之前，ISAC 决议对 VHDL 的所有修订版进行了修复，该决议确定显式定义的运算符始终重载隐式定义的运算符，而不会产生任何歧义.我注意到，即使是 VHDL 常见问题解答在这个问题上也已过时.

Note, some suggest that the overloading of ">" and friends in numeric_std_unsigned/std_logic_unsigned is illegal. This was a very conservative interpretation of 1076 prior to VHDL-2008. It was fixed for all revisions of VHDL with an ISAC resolution prior to VHDL-2008 that determined that explicitly defined operators always overload implicitly defined operators without creating any ambiguity. I note that even the VHDL FAQ is out of date on this issue.

4) 正式但实用.永远不要使用 std_logic_vector.仅使用数字类型，例如来自包 ieee.numeric_std 的无符号和有符号.有符号和无符号类型也支持与整数的比较.

4) Be formal, but practical. Never use std_logic_vector. Only use numeric types, such as unsigned and signed from package ieee.numeric_std. Types signed and unsigned also support comparisons with integers.

我可能遗漏了一些策略.

There are probably a few strategies I left out.

请注意，VHDL-2008 引入了匹配运算符，通过不为没有数字解释的类型定义它们，也解决了这个问题.这些运算符是: ?=, ?/=, ?>, ?>=, ?<, ?<=

Note that VHDL-2008 introduces matching operators which also address this issue by not defining them for types that do not have a numeric interpretation. These operators are: ?=, ?/=, ?>, ?>=, ?<, ?<=

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