对std_logic_vector进行位移位，同时保持精度并转换为有符号 [英] Bitshifting std_logic_vector while keep precision and conversion to signed

问题描述

在VHDL中，我想要一个14位输入并在末尾附加"00"，以便给我一个16位数字，该数字是14位输入乘以4的乘积，然后将其放入一个17位带符号变量中，这样为正(输入始终为正).我该怎么办?

In VHDL I want to take a 14 bit input and append '00' on the end to give me a 16 bit number which is the 14 bit input multiplied by 4 and then put this into a 17 bit signed variable such that it is positive (the input is always positive). How should I go about this?

像这样吗? shiftedInput <= to_signed('0' & input & '00', 17);

或者也许是这样? shiftedInput <= to_signed(input sll 2, 17);

还是这个? shiftedInput <= to_signed(input & '00', 17);

是否看到它得到的std_logic_vector是16位并且有符号变量是17位，因此假定最高有效位(歌唱位)是0?

Does it see that the std_logic_vector it's getting is 16 bit and the signed variable is 17 bit and therefore assume the most significant bit (the singing bit) is 0?

还是我必须这样做? shiftedInput <= to_signed('0' & input sll 2, 17);

Or do I have to do this? shiftedInput <= to_signed('0' & input sll 2, 17);

例如如果我将14位数字17读为std_logic_vector [即(00 0000 0001 0001)]，应将其转换为带符号的+68. [IE. (0 0000 0000 0100 0100)]

e.g. If I read in the 14 bit number 17 as a std_logic_vector [i.e. (00 0000 0001 0001)] it should be converted to the signed number +68. [i.e. (0 0000 0000 0100 0100)]

推荐答案

std_logic_vector是兼容，其类型为numeric_std.因此，类型转换函数是signed(不是在整数和向量之间转换的to_signed):

std_logic_vector is compatible with the type signed of numeric_std. So, the type conversion function is signed (not to_signed that converts between integers and vectors):

shiftedInput <= signed('0' & input & "00");

应该做到.请注意"00"而不是您的'00'.位字符串用双引号引起来，而位用单引号引起来.

should make it. Note the "00" instead of your '00'. Bit strings are double-quoted while bits are single-quoted.

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