VHDL 将字符串文字扩展到 std_logic_vector [英] VHDL extend string literal to std_logic_vector

问题描述

我正在尝试将像 B"101" 这样的字符串文字转换为 C_NO_OF_CHANNELS 位 std_logic_vector.

I am trying to convert a string literal like B"101" to C_NO_OF_CHANNELS bits std_logic_vector.

正在做:

library ieee, std, switch_core;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

std_logic_vector(resize(unsigned(B"101"), C_NO_OF_CHANNELS))

加注:

Type conversion (to UNSIGNED) can not have string literal operand.

推荐答案

在 Paebbels 的评论和 wahab 的回答之间，几乎有两种工作方式可以将位字符串文字转换为调整大小的 std_logic_vector.两种方法都可以修正.

Between Paebbels comment and wahab's answer there are almost two working ways of converting the bit string literal to a resized std_logic_vector. Both methods can be corrected.

Paebbels 的(更正)方法需要先将位串转换为整数值，然后使用 to_unsigned 将(自然)值转换为无符号，然后类型转换为 std_logic_vector:

Paebbels' (corrected) method requires converting the bit string to an integer value first then using to_unsigned to convert the (natural) value to unsigned, then type converting to std_logic_vector:

std_logic_vector(to_unsigned (to_integer(unsigned'(B"101")), C_NO_OF_CHANNELS)); -- works

wahab 更正和简化的方法(使用限定表达式):

wahab's corrected and simplified method (using a qualified expression):

std_logic_vector(resize(unsigned'(B"101"), C_NO_OF_CHANNELS)); -- works

一个最小、完整且可验证的示例，可用于演示两者:

A Minimal, Complete, and Verifiable example that can be used to demonstrate both:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity extend is
end entity;

architecture foo of extend is
constant  C_NO_OF_CHANNELS:     natural := 42;
signal target: std_logic_vector (C_NO_OF_CHANNELS - 1 downto 0) := 
        -- std_logic_vector(resize(unsigned(std_logic_vector'(B"101")), C_NO_OF_CHANNELS)); -- original - doesn't work
        -- std_logic_vector(to_unsigned (to_integer(unsigned'(B"101")), C_NO_OF_CHANNELS)); -- works
        std_logic_vector(resize(unsigned'(B"101"), C_NO_OF_CHANNELS)); -- works
begin
end architecture;

请注意 C_NO_OF_CHANNELS 的常量值已提供.

Note a constant value for C_NO_OF_CHANNELS has been provided.

更正后的 wahab 表达式使用限定表达式来消除两个可能的调整大小函数(有符号和无符号)之间的歧义，其中任一函数的结果能够被类型转换为 std_logic_vector.

The corrected wahab expression uses a qualified expression to disambiguate between two possible resize functions (signed and unsigned) the result of either capable of being type converted to std_logic_vector.

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