签名到 std_logic_vector，切片结果 [英] signed to std_logic_vector, slice results

问题描述

我需要取结果的绝对值，我只对最高有效位感兴趣.这就是我所做的:

I need to take the absolute value of a result and I am only interested in the most significant bits. This is what I have done:

data_ram_h <= std_logic_vector(abs(signed(resize(r4(calc_cnt - 2), data_ram_h'length) + r4(calc_cnt - 1) +
                    r4(calc_cnt) + r4(calc_cnt + 1) + r4(calc_cnt + 2) -
                    r2(calc_cnt - 2) - r2(calc_cnt - 1) - r2(calc_cnt) -
                    r2(calc_cnt + 1) - r2(calc_cnt + 2))))(11 downto 4);

我尝试检查语法，但出现此错误:

I try to check the syntax and I get this error:

type conversion std_logic_vector is not allowed as a prefix for an slice name.

data_ram_h 是一个正确维度的 std_logic_vector，abs 函数返回一个有符号的，转换为 std_logic_vector 应该没有问题.我使用的库是使用 ieee.numeric_std.all.

data_ram_h is a std_logic_vector of the right dimension, and the abs function returns a signed, to there shouldn't be problem in the conversion to std_logic_vector. The library I am using is use ieee.numeric_std.all.

我哪里错了?提前致谢 c:

Where am I wrong? Thanks in advance c:

推荐答案

类型转换是一种基本操作，恰好需要在其操作数表达式周围加上括号.还有一个问题，它的用途不是函数调用，所以它不能用作切片名称的前缀.

A type conversion is a basic operation that happens to require parentheses around it's operand expression. And there's the rub, it's use is not a function call, so it can't be used as a prefix for a slice name.

切片名称的前缀是函数调用或名称.(IEEE Std 1076-2008，5 种类型，5.1 通用，显式类型转换，8 名称，8.1 通用，8.5 切片名称).

A prefix for a slice name is either a function_call or a name. (IEEE Std 1076-2008, 5 Types, 5.1 General, explicit type conversion, 8 Names, 8.1 General, 8.5 Slice names).

如果是函数调用，您可以对结果进行切片.

If it was a function call you could slice the result.

另一方面，你可以切片`"abs"，所以切片然后进行类型转换:

On the other hand you can slice `"abs", so slice that and then do the type conversion:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity slice is
end entity;

architecture foo of slice is
    signal h_tmp: signed (11 downto 0);
    signal h_tmp_vec: std_logic_vector (11 downto 0);
    signal data_ram_h: std_logic_vector(7 downto 0);
    signal calc_cnt:     integer := 3;
    type r_array is array (0 to 15) of unsigned(15 downto 0);
    signal r2, r4: r_array := (others => (others => '0'));
begin


    data_ram_h<= std_logic_vector (
                     "abs"(signed(resize(r4(calc_cnt - 2), data_ram_h'length) + r4(calc_cnt - 1) +
                      r4(calc_cnt) + r4(calc_cnt + 1) + r4(calc_cnt + 2) -
                      r2(calc_cnt - 2) - r2(calc_cnt - 1) - r2(calc_cnt) -
                      r2(calc_cnt + 1) - r2(calc_cnt + 2)))(11 downto 4)
                      );

end architecture;

使用 abs 作为函数调用要求您使用它的声明名称，即 "abs".

Using abs as a function call requires you use it's declared name which is "abs".

我只是猜测这里的一些声明，所以我不能保证这在您的代码中有效.上面的例子确实分析、阐述和运行，表明子类型范围是兼容的.

I'm just guessing at some declarations here, so I can't guarantee this works in your code. The above example does analyze, elaborate and run which says the subtype ranges are compatible.

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