VHDL：查找/报告整数的位宽/长度（与std_logic_vector相比）？ [英] VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?

问题描述

说我需要一个信号来表示从0到5的数字;显然这需要表示3比特的std_logic（即如果MAXVAL = 5，则bitwidth = { wcalcfloor（logtwo（$ MAXVAL））+ 1 } 的）。

Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented (i.e if MAXVAL=5, then bitwidth= {wcalc "floor(logtwo($MAXVAL))+1"}).

我知道我可以这样做：

SIGNAL myLogicVector : STD_LOGIC_VECTOR(2 downto 0) := 5; 

我将使用它明确指定三个std_logic'位'的数组，并设置初始值;然后我可以使用REPORT打印出长度（在本例中为3）：

with which I'd explicitly specify an array of three std_logic 'bits', and set initial value; then I could use REPORT to print out the length (in this case, 3):

report("Bit width of myLogicVector is "& integer'image(myLogicVector'length));

到目前为止，非常好。但是，假设我使用整数（数字）类型：

So far, so good. But, let's say I use an integer (number) type instead:

SIGNAL myInteger : NATURAL range 0 to 5 := 5;

我猜这里的'编译'（'合成器'）会自动推断它需要3位存储长度，因为这个整数的范围是0到5之间的值。如果是这种情况，我的问题是：是否有可能以某种方式打印出来报告中的位宽/长度/大小？

I'm guessing that here the 'compiler' ('synthesizer') would automatically infer that it needs 3 bits of storage length, as this integer is ranged with values between 0 and 5. If that is the case, my question is: is it possible to somehow print out this bit width/length/size in a REPORT?

当然，诀窍是这样的：

report("Bit width of myInteger is "& integer'image(myInteger'length));

...将失败（例如，使用 HDLParsers：3389 - 属性的前缀 length必须是一个数组对象），因为据我所知，所有这些属性，如'length 和'范围仅适用于数组（了解VHDL属性），而整数（自然）不是数组 - 它是数字 :)（ VHDL向量整数转换问题）

... will fail (say, with "HDLParsers:3389 - Prefix of attribute 'length must be an array object"), since as far as I gather, all these attributes like 'length and 'range are applicable only to arrays (Understanding VHDL Attributes), whereas an integer (natural) is not an array - it is a number :) (VHDL vector integer conversion question)

再次，我知道我可以使用log2（从最大值计算无符号变量的宽度？） - 但是我想要的只是快速看到（在合成期间）'合成'有多少'位' sizer'被分配用于最终的综合设计，因此大约将在最终FPGA资源中使用多少（，特别是如果我使用'泛型'以某种方式计算整数的特定最大值 ）。

Again, I'm aware I could possibly utilize a log2 (Computing the width of an unsigned variable from maximum value?) - but what I'd like is just to see quickly (during synthesis) how many 'bits' the 'synthesizer' allocated for an eventual synthesized design, and thus approx how much would be used in terms of final FPGA resources (especially if I'd use 'generics' to somehow calculate a particular max value for an integer).

好的，预先感谢任何回复，
干杯！

Well, thanks in advance for any responses, Cheers!

编辑：一点上下文：我正在使用ISE Webpack 9.2;我正在尝试使用'通用'变量/常量作为参数，然后使用公式计算计数器的最大值。这个计算，我猜想发生在'编译'时（在ISE中是'Synthesize' - 而不是'实现设计'），所以它就在这里我希望报告消息发生（我实际上得到了对于std_logic_vector来说，它们在合成日志中是正确的 - 然而，同样的报告消息也出现在行为模拟的开始，这很好）。

a bit of context: I'm using ISE Webpack 9.2; I'm trying to use 'generic' variables/constants as parameters, and then use equations to calculate max values for counters. This calculation, I guess occurs at 'compile' time (which would be 'Synthesize' in ISE - not 'Implement Design'), and so it is here where I want the report messages to occur (and I in fact got them so, for std_logic_vector proper, in the synthesis log - however, the same report messages for me occur at start of behavioral simulation too, which is fine).

这些报告消息的目的是确保我的方程式都正常，并且合成器不会尝试推断32位计数器 - 即使我想数从0到5 :) :)

And the goal of these report messages is to make sure both that my equations are OK, and that the synthesizer will not try to infer a 32-bit counter - even if I want to count just from 0 to 5 :)

推荐答案

我猜这里是'compiler'
（'synthesizer'）将自动
推断它需要3位存储
长度，因为这个整数的范围是0到5之间的
值

I'm guessing that here the 'compiler' ('synthesizer') would automatically infer that it needs 3 bits of storage length, as this integer is ranged with values between 0 and 5

根据规范应该，但不是必需的。来自IEEE 1076.6-2004：

According to the spec it should, but it is not required. From IEEE 1076.6-2004:

1.3术语

单词 表示严格遵守强制性要求，以符合标准，并且不允许任何
偏差（应等于）。
这个词用来表示某个行动方案是首选，但b b b不一定是必需的;

1.3 Terminology

The word shall indicates mandatory requirements strictly to be followed in order to conform to the standard and from which no deviation is permitted (shall equals is required to). The word should is used to indicate that a certain course of action is preferred but not necessarily required;

建议综合工具将具有整数子类型指示的信号或
变量转换为
对应位向量。如果范围不包含负
值，则该项应具有无符号二进制表示。如果
范围包含一个或多个负值，则该项应具有
二进制补码实现。向量应该具有与这些表示一致的最小
宽度。

It is recommended that a synthesis tool should convert a signal or variable that has an integer subtype indication to a corresponding vector of bits. If the range contains no negative values, the item should have an unsigned binary representation. If the range contains one or more negative values, the item should have a twos-complement implementation. The vector should have the smallest width consistent with these representations.

综合工具应支持整数类型以及正，负和
无约束（通用）整数
，其范围在-2 147 483 648到+2 147 483 647（包括成功映射32位二进制补码数的范围
）范围内

The synthesis tool shall support integer types and positive, negative, and unconstrained (universal) integers whose bounds lie within the range –2 147 483 648 to [phone] inclusive (the range that successfully maps 32 bit twos-complement numbers)

示例：INTEGER范围9到10应使用
等效向量长度为​​4位进行合成，就好像已定义
一样子类型指示为INTEGER范围0到15。

Example: "INTEGER range 9 to 10" should be synthesized using an equivalent vector length of 4 bits, just as if it had been defined with a subtype indication of "INTEGER range 0 to 15".

我可以肯定地说至少有一个综合工具没有以这种方式使用 range ，因为我必须调试正式的验证错误比较。

I can say definitively at least one synthesis tool does not use range in this manner as I had to debug the formal verification miscompares.

对于Xilinx FPGA，XST综合报告将告知哪些存储元件有未使用的位，而不是简单的电线。

For Xilinx FPGAs, the XST synthesis report will tell which storage elements have unused bits, but not simple wires.

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