将枚举类型转换为 std_logic_vector VHDL [英] Convert enum type to std_logic_vector VHDL

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问题描述

我想知道是否可以将枚举类型(如 FSM 状态)转换为 std_logic_vector 或整数.我正在使用 OSVVM 为 FSM 做一个测试平台,我想使用记分板包自动将预期状态与实际状态进行比较.

I want to know if it is possible to convert a enum type, like FSM states to std_logic_vector or integer. I'm doing a testbench with OSVVM for a FSM and I want to use the scoreboard package to automatically compare the expected state with the actual one.

谢谢!

推荐答案

要转换为整数,请使用:

To convert to integer, use:

IntVal := StateType'POS(State) ; 

从那里,很容易转换为 std_logic_vector,但我更喜欢尽可能使用整数,因为它们的存储空间比 std_logic_vector 小.为了验证,当值小于 32 位时,如果您开始更多地考虑整数会更容易.

From there, it is easy to convert to std_logic_vector, but I prefer to work with integers when possible as they are smaller in storage than std_logic_vector. For verification, it will be easier if you start to think more about integers when the value is less than 32 bits.

如果你需要它作为 std_logic_vector,你可以只使用 numeric_std:

If you need it as std_logic_vector, using only numeric_std you can:

Slv8Val := std_logic_vector(to_unsigned(IntVal, Slv8Val'length)) ; 

为了验证,我大量使用 numeric_std_unsigned,所以转换更容易:

For verification, I liberally use numeric_std_unsigned, so the conversion is a easier:

Slv8Val := to_slv(IntVal, Slv8Val'length) ; 

如果您有一个整数并希望将其转换回枚举值,您可以使用VAL".

In the event you have an integer and want to convert it back to a enumerated value, you can use 'VAL.

State := StateType'VAL(IntVal) ; 

在 OSVVM 中,我们使用具有解析值的记录来创建事务接口.我们有一个解析的整数类型(osvvm.ResolutionPkg.integer_max).我们使用 'POS(输入时)和 'VAL(输出时)通过记录传输枚举值.

In OSVVM, we use records with resolved values to create a transaction interface. We have a resoled types for integers (osvvm.ResolutionPkg.integer_max). We transfer enumerated values through the record using 'POS (as we put it in) and 'VAL (as we get it out).

注意不要将VAL"与VALUE"混淆.'VALUE 将字符串转换为值 - 与 'IMAGE 相反.

Note don't confuse 'VAL with 'VALUE. 'VALUE converts a string to a value - opposite to 'IMAGE.

您当然可以在 SynthWorks 的 OSVVM 课程中学到所有这些:)

You of course learn all of this in SynthWorks' OSVVM class :).

这篇关于将枚举类型转换为 std_logic_vector VHDL的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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