VHDL;如何在受约束的数组中约束不受约束的 std_logic_vector [英] VHDL; How do I constrain a unconstrained std_logic_vector within a constrained array

问题描述

考虑以下内容

type foo is (A, B, C);
type foo_vector is array (foo) of std_logic_vector;

我如何约束 foo_vector?如果我给它默认值，编译器似乎应该能够限制信号.

How do I constrain foo_vector? It seems like the compiler should be able to constrain the signal if I give it defaults.

signal bar : foo_vector : (others => x"0000"); 

但是编译器只是继续说信号不能不受约束"

But the compiler just continues to say "Signal cannot be unconstrained"

如果是这样，那么我如何限制这个信号?

If that's the case then how can I constrain this signal?

signal bar : foo_vector(?)(15 downto 0);

我正在使用 Lattice 编译器.

I am using the Lattice compiler.

或者，如果我这样做

type baz_vector is array (natural range <>) is std_logic_vector;

我尝试通过这样做来限制信号:

And I try to constrain the signal by doing this:

signal baz_vector_signal : baz_vector(1 downto 0)(15 downto 0);

代码编译通过.所以我知道编译器能够处理不受约束的数组(VHDL2008).

The code compiles. So I know that the compiler is capable of handling unconstrained arrays (VHDL2008).

推荐答案

您的代码片段没有提供最小的、可重现的例子.

Your code snippets don't provide a minimal, reproducible example.

您正在尝试为 std_logic_vector 类型的元素提供元素约束，而数组索引已受到约束.

You're attempting to provide an element constraint for the element of type std_logic_vector while the array index is already constrained.

这是可能的:

library ieee;
use ieee.std_logic_1164.all;

package cjc_pkg is
    type foo is (A, B, C);
    type foo_vector is array (foo) of std_logic_vector;
    signal bar: foo_Vector (open) (3 downto 0) := (others => (others => '0'));
end package;

使用在 IEEE Std 1076-2008 5.3.2 Array types, 5.3.2.1 General, (the BNF) 中找到的数组约束，用于声明信号 bar:

using an array constraint found in IEEE Std 1076-2008 5.3.2 Array types, 5.3.2.1 General, (the BNF) in the subtype indication for the declaration of signal bar:

受约束的数组定义::=
array element_subtype_indication

constrained_array_definition ::=
array index_constraint of element_subtype_indication

subtype_indication 是在 6.3 子类型声明中定义的，由可选的解析指示、类型标记和约束组成.这里我们处理的是不受约束的元素.

subtype_indication is defined 6.3 Subtype declarations and consist of a optional resolution indication, type mark and constraint. Here we are dealing with the unconstrained element.

从 6.3 开始:

约束::=
      range_constraint
    |数组约束
    |记录约束

constraint ::=
      range_constraint
    | array_constraint
    | record_constraint

元素约束::=
      array_constraint
    |记录约束

element_constraint ::=
      array_constraint
    | record_constraint

这让我们回到了 5.3.2.1:

which bounces us back to 5.3.2.1:

数组约束::=
     index_constraint [ array_element_constraint ]
    |( 打开 ) [ array_element_constraint ]

array_constraint ::=
      index_constraint [ array_element_constraint ]
    | ( open ) [ array_element_constraint ]

array_element_constraint ::= element_constraint
...
index_constraint ::= (离散范围{,离散范围})

array_element_constraint ::= element_constraint
...
index_constraint ::= ( discrete_range { , discrete_range } )

discrete_range ::= discrete_subtype_indication |范围

discrete_range ::= discrete_subtype_indication | range

数组约束可用于约束数组类型或子类型(参见 5.3.2.2 和 6.3).

An array constraint may be used to constrain an array type or subtype (see 5.3.2.2 and 6.3).

一个数组对象的特征在于索引的数量(数组的维数)；每个索引的类型、位置和范围；以及元素的类型和可能的约束.索引的顺序很重要.

An array object is characterized by the number of indices (the dimensionality of the array); the type, position, and range of each index; and the type and possible constraints of the elements. The order of the indices is significant.

您可以使用 (open) 作为空间持有者来跳过受约束的索引，从而保留受约束索引的顺序重要性.

You can use (open) as a space holder to skip over a constrained index preserving the order significance of the constrained index.

该示例将使用 -2008 兼容的 VHDL 实现进行分析.

The example will analyze with a -2008 compatible VHDL implementation.

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