VHDL - 从HEX文件中初始化std_logic_vector数组 [英] VHDL - init std_logic_vector array from HEX file

问题描述

  type memory_array是std_logic_vector（7 downto）的数组（31 downto 0） 0）; 
信号RAM：memory_array; 
  

我想从HEX文件中初始化它的内容。我想知道如何读取文件：

pre $ ram_init：process $ b $ file file_ptr：text;
变量line_text：string（1 to 14）;
变量line_num：行;
变量lines_read：integer：= 0;
变量char：character;
变量tmp_hexnum：string（1 to 2）;
begin
file_open（file_ptr，../ RAM.HEX，READ_MODE）;
while（not endfile（file_ptr））循环
readline（file_ptr，line_num）;
READ（line_num，line_text）;
if（lines_read <32）then
tmp_hexnum：= line_text（10 to 11）;
- ram（lines_read）< = tmp_hexnum;
lines_read：= lines_read + 1;
等待10 ns;
end if;
结束循环;
file_close（file_ptr）;
等待;
结束进程;

问题是（如果上面的代码有效，我甚至不知道）将tmp_hexnum字符串转换为std_logic_vector。

请耐心等待，VHDL初学者。

解决方案第一个错误是使用一个过程：如果你尝试综合这个设计，那么这个过程在设计建立和运行之前不会做任何事情;读取文件为时已晚！

相反，将init代码封装在一个函数中，并使用它来初始化内存

  signal ram：memory_array：= my_ram_init（filename =>../RAM.HEX）; 
  

这将在模拟中起作用，许多综合工具会推断RAM并正确初始化它。如果你声明一个常量而不是一个信号，这将创建一个ROM而不是一个RAM。

无论如何，函数看起来有点像

  function my_ram_init（filename：string）return memory_array is 
 variable temp：memory_array; 
  - 其他变量
 begin 
 file_open（...）; 
  - 在函数体
 file_close（...）上有一个很好的句柄; 
 return temp; 
结束功能; 
  

留下原始问题：

  temp（lines_read）<= to_slv（tmp_hexnum）; 
  

写入to_slv函数。这些应该有一个标准的图书馆，但由于某种原因，没有普遍接受的图书馆。所以，这是一个开始...
$ b $ pre $函数to_slv（tmp_hexnum：字符串）返回std_logic_vector是
变量temp：std_logic_vector （7 downto 0）;
可变数字：自然;
begin
for tmp_hexnum'range loop
case tmp_hexnum（i）is
when'0'..'9'=>
digit：= Character'pos（tmp_hexnum（i）） - Character'pos（'0'）;
当'A'..'F'=>
digit：= Character'pos（tmp_hexnum（i）） - Character'pos（'A'）;
当others =>数字<= 0;
最终情况;
temp（i * 4 + 3 downto i * 4）：= std_logic_vector（to_unsigned（digit））;
结束循环;
return temp;
结束功能;

I have simple "RAM" implemented as:

type memory_array is array(31 downto 0) of std_logic_vector(7 downto 0);
signal ram : memory_array;

I would like to init it's content from HEX file. I wonder about reading the file like:

ram_init: process
    file file_ptr : text;
    variable line_text : string(1 to 14);
    variable line_num : line;
    variable lines_read : integer := 0;
    variable char : character;
    variable tmp_hexnum : string(1 to 2);
begin
    file_open(file_ptr,"../RAM.HEX",READ_MODE);
    while (not endfile(file_ptr)) loop
        readline (file_ptr,line_num);
        READ (line_num,line_text);
        if (lines_read < 32) then
            tmp_hexnum := line_text(10 to 11);
            -- ram(lines_read) <= tmp_hexnum;
            lines_read := lines_read + 1;
            wait for 10 ns;
        end if;
    end loop;
    file_close(file_ptr);
    wait;
end process;

The problem is (if this code above would works, which I don't even know), how to convert the tmp_hexnum string to std_logic_vector.

Please have patience with me, VHDL beginner.

解决方案

The first mistake is to use a process : if you attempt to synthesise the design, the process won't do anything until the design is built and running; which is far too late to read a file!

Instead, wrap the init code in a function, and use that to initialise the memory

signal ram : memory_array := my_ram_init(filename => "../RAM.HEX");

This will work in simulation, and many synthesis tools will infer a RAM and initialise it correctly. If you declared a constant instead of a signal, this would create a ROM instead of a RAM.

Anyway the function looks a bit like

function my_ram_init(filename : string) return memory_array is
   variable temp : memory_array;
   -- other variables
begin
   file_open(...);
   -- you have a good handle on the function body
   file_close(...);
   return temp;
end function;

leaving you with the original problem :

temp(lines_read) <= to_slv(tmp_hexnum);

writing the to_slv function. There ought to be a standard library of these, but for some reason there isn't a universally accepted one. So, here's a start...

function to_slv (tmp_hexnum : string) return std_logic_vector is
   variable temp  : std_logic_vector(7 downto 0);
   variable digit : natural;
begin
   for i in tmp_hexnum'range loop
      case tmp_hexnum(i) is
      when '0' .. '9' => 
         digit := Character'pos(tmp_hexnum(i)) - Character'pos('0');
      when 'A' .. 'F' => 
         digit := Character'pos(tmp_hexnum(i)) - Character'pos('A');
      when others => digit <= 0;
      end case;
      temp(i*4+3 downto i*4) := std_logic_vector(to_unsigned(digit));
   end loop;
   return temp;
end function;

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