二进制串行加法器 - VHDL [英] Binary serial adder - VHDL

问题描述

我正在尝试使用结构描述在 VHDL 中设计一个 32 位二进制串行加法器.加法器应使用全加器和 d 锁存器.我的看法是:

I'm trying to design a 32bit binary serial adder in VHDL, using a structural description. The adder should make use of a full adder and a d-latch. The way I see it is:

全加器:

architecture Behavioral of FullAdder is
begin

s <= (x xor y) xor cin;
cout <= (x and y) or (y and cin) or (x and cin);
end Behavioral;

D-Latch:

architecture Behavioral of dLatch is
begin
state: process(clk)
begin
    if(clk'event and clk = '1') then
        q <= d;
    end if;
end process;
end Behavioral;

串行加法器:

add: process ( clk )
    variable count : integer range 0 to 31;
        variable aux : STD_LOGIC;
        variable aux2 : STD_LOGIC;
    begin
        if(clk'event and clk = '1') then
        fa: FullAdder port map(x(count), y(count), aux, s(count), aux2);
                    dl: dLatch port map(clock, aux2, aux);
        count := count + 1; 
    end if;
     end process;

但是，它似乎不起作用.另外，流水线串行加法器的最简单方法是什么?

However, it doesn't seem to work. Also, what would be the simplest way to pipeline the serial adder?

推荐答案

对于串行加法器的流水线，最好的方法是将加法器和 d 触发器一个接一个地连接起来.因此，您可以将第一个加法器的 cout 作为触发器的输入.该触发器的输出将是下一个加法器的 cin，依此类推.不过要小心，因为您还必须对每个加法器的 s 以及输入的每一位进行流水线处理，方法是将几个 d 触发器排成一行，以便将它们复制到各个流水线阶段.

For pipelining the serial adder, the best way is to connect the adders and d flip-flops one after the other. So, you would have the cout of the first adder be the input of a flip-flop. The output of that flip-flop will be the cin of the next adder and so on. Be careful though, because you will also have to pipeline the s of each adder, as well as each bit of the input, by essentially putting several d flip-flops in a row to copy them through the various pipeline stages.

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