二进制补码矢量VHDL的左移 [英] left shifting of a two's complement vector VHDL
问题描述
我正在尝试解决一些问题，我必须将名为A的8位向量转换为2A(A + A).
I'm trying to solve some exercises, I have to shift a 8-bit vector named A into 2A (A+A).
我对此的解决方案是:(A(7) and '1') & A(6 downto 0) & '0';
my soluction for this is: (A(7) and '1') & A(6 downto 0) & '0';
之后，我用这种方式对A进行二进制补码:
after this I made a two's complement of A in this way:
entity complementare is
port(a: in std_logic_vector(7 downto 0);
b: out std_logic_vector(7 downto 0));
end complementare;
architecture C of complementare is
signal mask, temp: std_logic_vector(7 downto 0);
component ripplecarry8bit is
port(a,b: std_logic_vector(7 downto 0);
cin: in std_logic;
cout: out std_logic;
s: out std_logic_vector(7 downto 0));
end component;
begin
mask<="11111111";
temp<=a nand mask;
rc: ripplecarry8bit port map(temp, "00000001", '0', cout, b);
end C;
--if you need I post ripplecarry code but consider it as a generic adder
要获得-2A (-A-A)，我正在考虑这样做:
To get -2A (-A-A) I was thinking to do this:
signal compA: std_logic_vector(7 downto 0);
compA: complementar port map(A, compA);
--shifting
(compA(7) and '1') & compA(6 downto 0) & '0'; -- -A
现在，我的主要疑问是关于-A的问题，在使用了互补运算符并获得compA之后，我必须将8位向量扩展为9位向量(因为我的输出必须是9位向量)，想这样做，但我对此表示怀疑:
Now, my main doubt is about -A, after using complementar and after getting compA, I have to extend 8-bit vector into 9-bit vector (cause my output has to be 9-bit vector), I was thinking to do this but I have doubts:
'1' & compA; --or should I just append compA to a '0' value?
推荐答案
针对您的问题的简单带符号算术解决方案:
对于信号A，它是大小为C_SIZEOF_A
Simple signed arithmetics solutions for your problem :
For a signal A which is an std_logic_vector of a size C_SIZEOF_A
signal A : std_logic_vector(C_SIZEOF_A-1 downto 0);
要获得等于-A(相同大小)的信号:
To get a signal equal to -A (same size):
对信号值进行补码，然后在此结果中加一个:
Complement the signal value and add one to this result:
signal minus_A : std_logic_vector(C_SIZEOF_A-1 downto 0);
minus_A <= (not A) + 1; -- Warning here !!!
警告:未为std_logic_vector定义'+'运算符.您可以使用自己喜欢的解决方案进行添加.我故意不想在这里给出解决方案，因为最简单的方法是使用signed信号，但是您说不能.
Warning: The '+' operator is not defined for std_logic_vector. You do the addition with the solution you prefer. I intentionaly don't want to give a solution here because the simplest one is to use signed signals but you said you can't.
将信号乘以2(有符号或无符号)
To multiply a signal by 2 (signed or unsigned)
添加一个空位作为LSB:
Add a null bit as LSB:
signal 2A : std_logic_vector(C_SIZEOF_A downto 0);
2A <= A & '0';
将信号扩展1位(有符号):
To extend a signal for 1 bit (signed) :
MSB是符号位.仅扩展此位:
The MSB is the sign bit. Extend only this bit:
signal A_extended : std_logic_vector(C_SIZEOF_A downto 0);
A_extended <= A(C_SIZEOF_A-1) & A;
将信号扩展1位(无符号):
To extend a signal for 1 bit (unsigned) :
这里没有符号位，只需添加"0"即可:
No sign bit here, simply add a '0':
signal A_extended : std_logic_vector(C_SIZEOF_A downto 0);
A_extended <= '0' & A;
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