Verilog 中的 Casex 与 Casez [英] Casex vs Casez in Verilog

查看:42
本文介绍了Verilog 中的 Casex 与 Casez的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

Verilog 中的 casexcasez 有什么区别?我搜索了一下,找到了这句话:

what is the difference between casex and casez in Verilog ? I have searched about it and find this sentence :

casez 处理 case 替代或 case 中的所有 z 值表达为不在乎.所有带有 z 的位位置也可以由 ?在那个位置.

casez treats all z values in the case alternatives or the case expression as don't cares. All bit positions with z can also represented by ? in that position.

casex 处理所有 x 和 z 值在 case 项或 case 表达式中为不

casex treats all x and z values in the case item or the case expression as don't

关心.

例如,第一个和第二个有什么区别:

for example , what is the difference between first one and second one:

1-

casez (instr)
7'b1zzzzzzz: // arithmetic
7'b01zzzzzz: // load-reg
7'b00zzzzzz: // store-reg
endcase

2-

 casex (instr)
    7'b1zxxxxzz: // arithmetic
    7'b01zzxxxx: // load-reg
    7'b00xxxzzz: // store-reg
    endcase

推荐答案

Verilog 语言参考手册(现已替换为 SystemVerilog LRM) 非常详细地解释了这一点.关键区别在于 case 表达式 instr 何时包含 x 或 z 值.请记住,casexcasez 都会查看 case item case 表达式 用于 x 和 z 值.我们将此称为对称比较,因为无关值可以出现在任一位置.

The Verilog Language Reference Manual (now replaced by the SystemVerilog LRM) explains this in great detail. The key difference is when the case expression instr contains x or z values. Remember that both casex and casez look at both the case item and the case expression for x and z values. We call this a symmetric comparison as don't care values can show up in either place.

因此,如果 instr 全部是 x,casez 中的任何项目都不会匹配,但是 casez 中的项目ALL>casex 会匹配,模拟器会选择第一项.类似地,如果 instr 都是 z,则 ALL 项目将匹配.我认为 casex 是一个无用的结构.

So if instr was all x's, none of the items in the casez would match, but ALL of the items in the casex would match, and a simulator would pick the first item. Similarly, if instr were all z's, then ALL items would match. I consider casex a useless construct.

SystemVerilog 用 case() inside 语句替换这两个语句.它使用非对称比较运算符 ==? 仅将 case item 中的 x 或 z 视为无关.

SystemVerilog replaces both statements with a case() inside statement. It uses an asymmetric comparison operator ==? that only treats an x or z in the case item as a don't care.

这篇关于Verilog 中的 Casex 与 Casez的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

查看全文
登录 关闭
扫码关注1秒登录
发送“验证码”获取 | 15天全站免登陆