系统 verilog 中的打包向量与解包向量 [英] packed vs unpacked vectors in system verilog

问题描述

查看我在 System Verilog 中维护的一些代码，我看到一些定义如下的信号:

Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this:

node [range_hi:range_lo]x;

以及其他定义如下:

node y[range_hi:range_lo];

我知道 x 被定义为打包，而 y 被定义为未打包.但是，我不知道这意味着什么.

I understand that x is defined as packed, while y is defined as unpacked. However, I have no idea what that means.

System Verilog 中打包和解包向量的区别是什么?

What is the difference between packed and unpacked vectors in System Verilog?

回应@Empi 的回答，为什么用 SV 编写的硬件设计师应该关心数组的内部表示?有没有我不应该或不能使用打包信号的时候?

Responding to @Empi's answer, why should a hardware designer who's writing in SV care about the internal representation of the array? Are there any times when I shouldn't or can't use packed signals?

推荐答案

本文提供了有关此问题的更多详细信息:http://electrosofts.c​​om/systemverilog/arrays.html，尤其是第 5.2 节.

This article gives more details about this issue: http://electrosofts.com/systemverilog/arrays.html, especially section 5.2.

压缩数组是一种将向量细分为子字段的机制，这些子字段可以作为数组元素方便地访问.因此，打包数组保证表示为一组连续的位.解压缩的数组可能会也可能不会如此表示.压缩数组与非压缩数组的不同之处在于，当压缩数组作为主数组出现时，它被视为单个向量.

A packed array is a mechanism for subdividing a vector into subfields which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits. An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.

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