为什么我应该在 System Verilog 中使用解包向量? [英] why should I use unpacked vectors in System Verilog?

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问题描述

跟进 this 关于 SV 中打包和解包向量之间区别的问题,为什么我要使用解包向量?
压缩向量具有非压缩向量所没有的这些优点:

Following up on this question about the difference between packed and unpacked vectors in SV, why would I ever want to use unpacked vectors?
Packed vectors have these advantages that unpacked vectors don't have:

  • 您可以对它们执行按位运算
  • 您可以对它们进行算术运算
  • 你可以把它们切片
  • 您可以将它们作为一个整体进行复制
  • 您可以使用打包的向量做任何事情(据我所知)
  • You can perform bit-wise operations on them
  • You can perform arithmetic operations on them
  • You can take slices of them
  • You can copy them as a whole vector
  • You can do anything you can with unpacked vectors (to the best of my knowledge)

解包向量比打包向量有什么优势?

What advantage do unpacked vectors have over packed vectors?

推荐答案

我喜欢使用 unpacked 的另一个原因.使用 unpacked,没有将整个数组名称视为变量并进行错误赋值的诱惑(和偶然的可能性).当您可能认为您正在访问元素 N 的 B 位时,也不可能从一个元素到另一个元素发生位溢出,但实际上您可能正在访问元素 N 的 K 位和元素 N+-1 的 BK 位..

There is another reason why I like to use unpacked. With unpacked, there is no temptation (and accidental possibility) of treating the whole array name as a variable, and make an erroneous assignment. There is also no possibility of bit-bleeding from one element to another, when you may be thinking you are accessing B bits of element N, but in reality you may be accessing K bits of element N and B-K bits of element N+-1..

我的理念是在打包维度中仅保留属于一起的事物作为信息单元".未打包维度中的所有其他内容.默认的思维应该是解包的,只打包你需要的.

My philosophy is to keep only the things that belong together as a "unit of information" in the packed dimension. Everything else in the unpacked dimension. The default thinking should be unpacked, and pack only what you need to.

例如,如果我有 9 个端口,每个端口有 21 位信息,我想将其声明为:

For example, if I have 9 ports, each with 21 bits of information, I would like to declare it as :

input logic [20:0] p1 [9];

20:0 部分构成了一个信息单元,一起分配和采样(名义上).将这些位分开将破坏协议或端口的特性.另一方面,将端口数从 9 更改为 16,不会影响每个端口中信息的性质,因此 9 个端口在我看来确实属于未打包维度.

The 20:0 part constitutes a unit of information, assigned and sampled together (nominally). Splitting those bits apart will destroy the protocol or the character of the port. On the other hand, changing the number of ports from 9 to, say, 16, is not going to affect the nature of the information in each port, so the 9 ports really belong in the unpacked dimension in my mind.

希望这可以给你一个思考的范式......在这个范式中,你会惊讶地发现有多少你一直认为是打包的东西开始出现未打包!!

Hope that might give you a paradigm to think along... In this paradigm, you would be surprised how many things start to appear unpacked that you always thought were packed !!

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