始终块中的 Verilog generate/genvar [英] Verilog generate/genvar in an always block

问题描述

我试图让一个模块通过 ISE 12.4 中的语法检查，但它给了我一个我不明白的错误.首先是代码片段:

I'm trying to get a module to pass the syntax check in ISE 12.4, and it gives me an error I don't understand. First a code snippet:

parameter ROWBITS = 4;

reg [ROWBITS-1:0] temp;

genvar c;
generate
    always @(posedge sysclk) begin
        for (c = 0; c < ROWBITS; c = c + 1) begin: test
            temp[c] <= 1'b0;
        end
    end
endgenerate

当我尝试语法检查时，我收到以下错误消息:

When I try a syntax check, I get the following error message:

ERROR:HDLCompiler:731 - "test.v" Line 46: 程序分配给非注册 <c>不允许.

ERROR:HDLCompiler:731 - "test.v" Line 46: Procedural assignment to a non-register <c> is not permitted.

我真的不明白为什么它会抱怨.c"不是电线，它是 genvar.这应该等同于完全合法的语法:

I really don't understand why it's complaining. "c" isn't a wire, it's a genvar. This should be the equivalent of the completely legal syntax:

reg [3:0] temp;

always @(posedge sysclk) begin
    temp[0] <= 1'b0;
    temp[1] <= 1'b0;
    temp[2] <= 1'b0;
    temp[3] <= 1'b0;
end

请不要评论关于如何在没有生成的情况下更容易编写此内容的评论.这是一个更复杂的代码段的简化示例，涉及多个 if 和对temp"的非阻塞赋值.另外，不要只是告诉我有更新版本的 ISE，我已经知道了.OTOH，如果您知道它已在更高版本的 ISE 中修复，请告诉我您知道哪个版本有效.

Please, no comments about how it'd be easier to write this without the generate. This is a reduced example of a much more complex piece of code involving multiple ifs and non-blocking assignments to "temp". Also, don't just tell me there are newer versions of ISE, I already know that. OTOH, if you know it's fixed in a later version of ISE, please let me know which version you know works.

推荐答案

需要在 generate 块内反转嵌套:

You need to reverse the nesting inside the generate block:

genvar c;
generate
    for (c = 0; c < ROWBITS; c = c + 1) begin: test
        always @(posedge sysclk) begin
            temp[c] <= 1'b0;
        end
    end
endgenerate

从技术上讲，这会生成四个 always 块:

Technically, this generates four always blocks:

always @(posedge sysclk) temp[0] <= 1'b0;
always @(posedge sysclk) temp[1] <= 1'b0;
always @(posedge sysclk) temp[2] <= 1'b0;
always @(posedge sysclk) temp[3] <= 1'b0;

在这个简单的例子中，四个 always 块和一个包含四个赋值的 always 块之间的行为没有区别，但在其他情况下可能会有.

In this simple example, there's no difference in behavior between the four always blocks and a single always block containing four assignments, but in other cases there could be.

在构建设计的内存表示(在模拟器的情况下)或映射到逻辑门(在综合工具的情况下)时，需要解决依赖于 genvar 的操作.always @posedge 在设计运行之前没有意义.

The genvar-dependent operation needs to be resolved when constructing the in-memory representation of the design (in the case of a simulator) or when mapping to logic gates (in the case of a synthesis tool). The always @posedge doesn't have meaning until the design is operating.

受某些限制，您可以在 always 块内放置一个 for 循环，即使是可合成的代码.对于合成，循环将展开.但是，在这种情况下，for 循环需要使用 reg、integer 或类似的.它不能使用genvar，因为在always 块中使用for 循环描述了在时钟的每个边沿发生的操作，而不是在设计细化过程中可以静态扩展的操作.

Subject to certain restrictions, you can put a for loop inside the always block, even for synthesizable code. For synthesis, the loop will be unrolled. However, in that case, the for loop needs to work with a reg, integer, or similar. It can't use a genvar, because having the for loop inside the always block describes an operation that occurs at each edge of the clock, not an operation that can be expanded statically during elaboration of the design.

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