我可以在 SystemVerilog 中的 initial 中使用 generate-endgenerate 块吗? [英] Can I use generate-endgenerate block inside initial in SystemVerilog?

问题描述

例如

initial
begin

generate
for(genvar i; i < 4; i++)
//Code
endgenerate

end //initial

我在使用 QuestaSim 时遇到错误.接近生成:语法错误，意外生成"

I'm getting error using QuestaSim with the concept. "Near generate: syntax error, unexpected generate "

推荐答案

No. generate 块在精化时间期间进行评估.而initial、always和其他程序块从零仿真时间开始，即运行时间.参考 Systemverilog IEEE 1800-2012:

No. generate blocks are evaluated during elaboration time. While initial,always and other procedural blocks start at zero simulation time, that is, run-time. Referring to Systemverilog IEEE 1800-2012 :

生成的方案在详细设计过程中进行评估.尽管生成方案使用类似于行为的语法语句，重要的是要认识到它们不执行模拟时间.

Generate schemes are evaluated during elaboration of the design. Although generate schemes use syntax that is similar to behavioral statements, it is important to recognize that they do not execute at simulation time.

它们在精化时进行评估，并且在模拟开始前确定结果.因此，所有生成方案中的表达式应为常量表达式，确定性在精化时间.

They are evaluated at elaboration time, and the result is determined before simulation begins. Therefore, all expressions in generate schemes shall be constant expressions, deterministic at elaboration time.

在 Verilog 中，实例化一个模块意味着向电路板添加额外硬件.

In Verilog, instantiating a module means adding extra hardware to the board.

必须在模拟开始之前(即在编译时)添加此硬件.您在运行时不能添加/删除硬件.您可以有条件地实例化一个模块或乘以实例化它，但绝不能在运行时进行.

This hardware must be added before simulation starts(i.e. at compile time). You can not add/remove hardware during run time. You can either conditionally instantiate a module or multiply instantiate it, but never at run time.

参考生成块语法错误问题关于你的错误的想法.另外，请参阅此问题以了解生成和 genvar .参考 IEEE 1800-2012第 27 章了解更多信息.

Refer generate block syntax error question for an idea about your error. Also, refer this question for generate and genvar understanding. Referring IEEE 1800-2012 Chapter 27 for more information.

编辑:

要创建和传递多个接口实例，接口实例的总数必须由一些参数或宏<控制/em>.您可以在 generate 块中的 for 循环中使用此参数来创建不同的实例，并使用不同的键设置每个实例，如下所示:

To create and pass multiple interface instances, the total number of interface instances must be governed by some parameter or macro. You can use this parameter in for loop in generate block to create distinct instances and set each of them using different key as follows:

  // Generate multiple instances of interface
  genvar i;
  generate
    for(i=0;i<NUM_OF_INTERFACES;i++)
    begin
      // Generate clk with different period for each instance
      always #(i+1) clk[i] = ~clk[i];

      inter in(clk[i]);  // Create multiple instances here

    initial
      begin
        // Set each and every instance
        uvm_config_db#(virtual inter)::set(null,"*",$sformatf("in_%0d",i),in);
      end
    end
  endgenerate

在 EDAPlayground Multiple Interface 链接中创建了一个完整的示例.创建多个实例可以参考这个问题.

A complete example is created at EDAPlayground Multiple Interface link. Creating multiple instances can be referred from this question.

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