枚举可以在 systemverilog 中输出吗? [英] Can enum be made an output in systemverilog?
问题描述
在 verilog 中,我可以这样做:
In verilog, I can do something like this:
module controller (
input rstb, clk, start,
output reg [1:0] state, next_state
);
parameter S_idle = 2'b00, S_1 = 2'b01, S_2 = 2'b11;
always @ (posedge clk, negedge rstb)
begin
if (!rstb) state <= S_idle;
else state <= next_state;
end
...
endmodule
但是在 systemverilog 中,这会产生错误,因为我声明了 state, next_state
两次:
But in systemverilog, this will generate an error since I declared state, next_state
twice:
module controller (
input rstb, clk, start,
output logic [1:0] state, next_state
);
enum logic [1:0] {S_idle, S_1, S_2} state, next_state;
always_ff @ (posedge clk, negedge rstb)
begin
if (!rstb) state <= S_idle;
else state <= next_state;
end
...
endmodule
我想我可以将我的输出端口重命名为 state_out, next_state_out
并将它们分配给 state, next_state
.有没有更简单的方法来使用枚举作为输出?
I suppose I could rename my output ports to state_out, next_state_out
and assign them to state, next_state
. Is there an easier way to use the enum as an output?
推荐答案
当使用用户定义的类型时,你应该使用 typedef
并将它们放在一个包中,以便它们可以在模块之间共享使用它们.否则,您会遇到类型不兼容分配错误.
When using user defined types, you should use a typedef
and put them in a package so they can be shared amongst the modules that use them. Otherwise you run into type incompatibility assignment errors.
package stuff;
typedef enum logic [1:0] {S_idle, S_1, S_2} state_t;
endpackage
module controller import stuff::*; (
input logic rstb, clk, start,
output state_t state, next_state
);
always_ff @ (posedge clk, negedge rstb)
begin
if (!rstb) state <= S_idle;
else state <= next_state;
end
...
endmodule
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