Verilog:内存块实例化 [英] Verilog : Memory block Instantiation

问题描述

我使用以下代码在Verilog中实例化了二维内存

I used the following code to instantiate 2-D memory in a verilog

reg  [15:0] data_pattern_even [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

reg  [15:0] data_pattern_ev [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

此实例在Simulation中可以正常运行，但在实际合成和RTL分析完成后无法正常工作

This instantiation worked all right in Simulation but failed to work when actually synthesised and RTL analysis done

有人可以向我详细说明这是怎么可能的吗?

Can anyone elaborate to me as in how that is possible?

推荐答案

对于Altera器件: https://www.altera. com/support/support-resources/design-examples/design-software/verilog/ver_ram.html

For Altera devices: https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_ram.html

对于Xilinx器件(由Paebbels给出): http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug901-vivado-synthesis.pdf (第3章，初始化RAM内容")

For Xilinx devices (as given by Paebbels): http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug901-vivado-synthesis.pdf (Chapter 3, "Initializing RAM Contents")

对于莱迪思的设备: http://www. gridsemi.com/~/media/LatticeSemi/Documents/UserManuals/EI/iCEcube2_2013-08_userguide.pdf?document_id=50165 (初始化推断的RAM")

For Lattice devices: http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/EI/iCEcube2_2013-08_userguide.pdf?document_id=50165 ("Initializing Inferred RAM")

对于Microsemi设备:

For Microsemi devices: http://www.microsemi.com/document-portal/doc_view/129865-ac162-ram-initialization-and-rom-emulation-in-proasic-sup-u-plus-u-sup-devices-app-note

与Google进行简短搜索后，我发现了这一点: 如何初始化推断的Block RAM(BRAM)的内容)

A short search with google and I found this: How to initialize contents of inferred Block RAM (BRAM) in Verilog

只需在Google上搜索它即可:-)

Just google it :-)

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