python myhdl包如何生成verilog初始块 [英] python myhdl package how to generate verilog initial block
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问题描述
主要来自myhdl示例的代码:
From the code mostly from the sample of myhdl:
from myhdl import Signal, intbv, delay, always, now, Simulation, toVerilog
__debug = True
def ClkDriver(clk):
halfPeriod = delay(10)
@always(halfPeriod)
def driveClk():
clk.next = not clk
return driveClk
def HelloWorld(clk, outs):
counts = intbv(3)[32:]
@always(clk.posedge)
def sayHello():
outs.next = not outs
if counts >= 3 - 1:
counts.next = 0
else:
counts.next = counts + 1
if __debug__:
print "%s Hello World! outs %s %s" % (
now(), str(outs), str(outs.next))
return sayHello
clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)
我希望它生成一个包含 initial
块的 verilog 程序,例如:
I expect it to generate a verilog program that contains an initial
block, like something:
module HelloWorld(...)
reg [31:0] counts;
initial begin
counts = 32'h3
end
always @(...
如何生成 initial
块?
请注意,在 old.myhdl.org/doku.php/dev:initial_values 的 google 缓存中,它链接到示例 https://bitbucket.org/cfelton/examples/src/tip/ramrom/.所以看起来应该支持该功能.但是 rom 示例生成静态 case 语句.那不是我要找的.
Note that on the google cache for old.myhdl.org/doku.php/dev:initial_values it links to example https://bitbucket.org/cfelton/examples/src/tip/ramrom/ . So it looks the feature should be supported. However the rom sample generates static case statements. That's not what I'm looking for.
推荐答案
三步解决:
- 更新到 master 上的最新 myhdl 或包含哈希
87784ad
的版本,该版本添加了问题#105
或#150
下的功能.作为 virtualenv 的示例,运行 git clone,然后是pip install -e
. - 将信号更改为列表.
- 在调用
toVerilog
之前设置toVerilog.initial_values=True
.
- Update to the latest myhdl on master or a version that contains the hash
87784ad
which added the feature under issue#105
or#150
. As an example for virtualenv, run a git clone, followed bypip install -e <path-to-myhdl-dir>
. - Change the signal to a list.
- Set
toVerilog.initial_values=True
before callingtoVerilog
.
代码片段如下.
def HelloWorld(clk, outs):
counts = [Signal(intbv(3)[32:])]
@always(clk.posedge)
def sayHello():
outs.next = not outs
if counts[0] >= 3 - 1:
counts[0].next = 0
else:
counts[0].next = counts[0] + 1
if __debug__:
print "%s Hello World! outs %s %s %d" % (
now(), str(outs), str(outs.next), counts[0])
return sayHello
clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
toVerilog.initial_values=True
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)
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