带生成语句的Verilog放置约束 [英] Verilog Placement Constraints with Generate Statements

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本文介绍了带生成语句的Verilog放置约束的处理方法,对大家解决问题具有一定的参考价值,需要的朋友们下面随着小编来一起学习吧!

问题描述

我正在尝试使用Generate语句生成彼此相邻放置的闩锁数组.我一直在尝试使用Xilinx约束"RLOC"来执行此操作,但没有成功.

I'm trying to generate an array of latches that are placed adjacent to each other using a Generate statement. I've been trying to use the Xilinx constraint "RLOC" to do this, but I haven't been successful.

下面的代码无法成功实现,但应说明我尝试获取的内容.以下代码的问题在于约束调用中的"i"未转换为字符串,这是该调用所要查找的内容.有人有这样做的经验吗?

The code below won't successfully implement, but should illustrate what I'm trying to obtain. The issue with the code below is that "i" in the constraint call isn't being converted into a string, which is what the call is looking for. Does anyone have experience doing this?

我正在使用带有Xilinx ISE 10.1.03的Virtex4进行综合和实现.我不完全确定我使用的是Verilog的哪个版本,但我认为它是Verilog2001.如果有人能告诉我如何检查我使用的Verilog的版本,我将不胜感激.

I'm using a Virtex4 with Xilinx ISE 10.1.03 for synthesis and implementation. I'm not entirely sure what version of Verilog I'm using, but I think it's Verilog 2001. I'd be grateful if someone could also tell me how to check what version of Verilog I'm using.

  genvar i;
  generate
    for (i = 0; i < DATA_WIDTH; i = i + 1)
    begin : LATCH
      (* RLOC = {"X0Y", i} *)
      latch inst_latch (
        .d        (data_in[i]),
        .gate     (gate), 
        .reset    (reset),
        .q        (data_out[i])
      ); 
    end
  endgenerate

推荐答案

当传递给RLOC时,我最终使用参数化宏将生成变量替换为字符串.这是一个解决方法,如果我早些时候看到过,我很可能会使用Greg的解决方案.

I ended up using parameterized macros to replace the generate variable with a string when passed to RLOC. It's quite a workaround, and I most likely would have used Greg's solution had I seen it earlier.

无论如何,如果人们真的感兴趣,请使用宏:

Anyway, in case people are actually interested, the macros :

parameter DIGITS = "9876543210";

`define THOUSANDS(x) (x / 1000)
`define  HUNDREDS(x) ((x - (`THOUSANDS(x) * 1000)) / 100)
`define      TENS(x) ((x - (`THOUSANDS(x) * 1000) - (`HUNDREDS(x) * 100)) / 10)
`define      ONES(x) (x - (`THOUSANDS(x) * 1000) - (`HUNDREDS(x) * 100) - (`TENS(x) * 10))

`define     TO_STRING(x) (DIGITS[((8 * (x + 1)) - 1) : (8 * x)])
`define VAR_TO_STRING(x) ({`TO_STRING(`THOUSANDS(x)), `TO_STRING(`HUNDREDS(x)), `TO_STRING(`TENS(x)), `TO_STRING(`ONES(x))})

宏THOUSANDS(),HUNDREDS(),TENS()和ONES()返回在 x 中找到的数千个,数百个,数十个和十个数.这些宏应始终返回1位数的值.

The macros THOUSANDS(), HUNDREDS(), TENS(), and ONES() return the number of thousands, hundreds, tens, and ones found in x. These macros should always return 1 digit values.

TO_STRING()接受约1位数字的值,并通过返回一部分参数 DIGITS 将其转换"为字符串.

TO_STRING() takes some 1 digit value and "converts" it to a string by returning a portion of parameter DIGITS.

VAR_TO_STRING()结合使用上述所有宏,以将任意4位整数转换为等效的字符串.问题中的代码将被替换为:

VAR_TO_STRING() uses all of the above macros in conjunction to convert any 4 digit integer into its string equivalent. The code in the question would then be replaced by :

genvar i;
generate
  for (i = 0; i < DATA_WIDTH; i = i + 1)
  begin : LATCH
    (* RLOC = {"X0Y", `VAR_TO_STRING(i)} *)
    latch inst_latch (
      .d        (data_in[i]),
      .gate     (gate), 
      .reset    (reset),
      .q        (data_out[i])
    ); 
  end
endgenerate

这篇关于带生成语句的Verilog放置约束的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持IT屋!

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