在Verilog中实例化模块 [英] Instantiation of a module in verilog

问题描述

在verilog文件中实例化模块时遇到错误.我是这样实例化的:

I am getting an error in instantiating a module in verilog file. I am instantiating like this:

module lab3(input clk,set,reset,plus,minus,start,button,output reg [3:0]led,output reg [6:0]y);

wire [3:0] indicesgu[3:0];
reg [1:0] going;
reg alsogoing,yes;


if (going==1 && alsogoing)
begin
 up_counter up_0 ( 
 indicesgu  ,
 indices    ,
 alsogoing
 );
end

endmodule

endmodule

，我的up_counter模块开始于:

and my up_counter module starts as:

module up_counter(input [3:0] indices_in [3:0],output [3:0]indices[3:0],output alsogoing);

reg [3:0]indices[3:0];
reg [2:0]current,setting;

endmodule

endmodule

当我尝试在Xilinx中进行编译时，它表示意外的令牌up_counter. 预先感谢.

when I try to compile in Xilinx, it says unexpected token up_counter. Thanks in advance.

推荐答案

您的lab3模块存在一些问题.

There are several problems with your lab3 module.

1. 您最后需要一个endmodule.
2. 您不应在if内部实例化up_counter. Verilog不支持这样的条件实例.
3. 您需要在实例名称up_0之后添加一个开头括号.

1. You need an endmodule at the end.
2. You should not instantiate up_counter inside an if. Verilog does not support conditional instances like that.
3. You need an opening paren after the instance name up_0.

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