System Verilog 中的覆盖点 [英] Coverpoints in System Verilog

问题描述

是否可以根据参数从特定组中排除某些覆盖点?

Is it possible to exclude some coverpoints from a particular group based on a parameter?

covergroup NEW (string for_exclusion) @ (clk);
option.per_instance = 1;
option.comment = for_exclusion;

apples: coverpoint (available) { bins hit1 = {1'b1};}
bananas: coverpoint ({not_available, less}) {bins hit1 = {1'b1};}
oranges: coverpoint ({available, less}) {bins hit1 = {1'b1};}
rose: coverpoint ({available, flower}) {bins hit1 = {1'b1};}

这是原始文件的一小部分.我想根据我已经在模块中传递的参数 parameter IDENTITY = 2'b00 从这个封面组中排除 'rose'.有没有办法做到这一点?(如果有语法错误，请忽略.我目前不担心)

This is small part of the original file. I want to exclude 'rose' from this covergroup based on parameter parameter IDENTITY = 2'b00 which I have already passed in the module. Is there a way to do this? (Please ignore syntax errors, if any. I am not worried about them at the moment)

我试过用这个，但没有用.

I tried using this but it did nt work.

covergroup NEW (string for_exclusion) @ (clk);
option.per_instance = 1;
option.comment = for_exclusion;

apples: coverpoint (available) { bins hit1 = {1'b1};}
bananas: coverpoint ({not_available, less}) {bins hit1 = {1'b1};}
oranges: coverpoint ({available, less}) {bins hit1 = {1'b1};}

generate
if (IDENTITY = 2'b01) begin
rose: coverpoint ({available, flower}) {bins hit1 = {1'b1};}
end
endgenerate`

推荐答案

您不能在声明另一个构造的过程中使用 generate.您能否将该覆盖点分离到另一个覆盖组中，而不是根据另一个参数对其进行构建/采样?

You cannot use generate in the middle of declaring another construct. Can you separate that coverpoint out into another covergroup and not construct/sample it based on the other parameter?

另一种选择是根据参数将coverpoint的权重设置为0.您可以在构建覆盖组之前或之后在过程代码中执行此操作.

Another choice is to set the weight of the coverpoint to 0 based on the parameter. You can do this in procedural code before or after constructing the covergroup.

if (IDENTITY != 2'b01)
  NEW::rose::type_option.weight = 0;

或在掩护点内

rose: coverpoint ({available, flower}) {
  bins hit1 = {1'b1};
  option.weight = (IDENTITY == 2'b01};
}

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