Verilog多维reg错误 [英] verilog multi-dimensional reg error

问题描述

此语句：

reg [7:0] register_file [3:0] = 0;

产生此错误：

Error (10673): SystemVerilog error at simpleprocessor.v(27): assignments to unpacked arrays must be aggregate expressions

首先，我使用的是Verilog，而不是SystemVerilog，为什么会给我一个SystemVerilog错误？

First of all I am using Verilog, not SystemVerilog, so why is it giving me a SystemVerilog error?

第二，什么？错误的原因是什么，我该如何解决？我在使用一个非常简单的处理器的时候就使用它，将内部工作寄存器表示为内存的一个多维度数组。

Second of all, what is the cause of this error, and how can I fix it? I am using it in my desgin of a very rudementary processor to represent the internal working registers as a multidemmnsional array of memory.

我的寄存器可以直接访问从说明。例如以下行：

It would be such that my registers are accessible directly from the instructions. For example this line:

register_file[instruction[5:4]] <= register_file[instruction[3:2]] + register_file[instruction[1:0]];

但是它不起作用。有想法吗？

But it's not working. Any ideas?

推荐答案

从SystemVerilog LRM：

From the SystemVerilog LRM:

术语打包数组用于表示在数据标识符名称之前声明的维。术语解压缩数组用于表示在数据标识符名称之后声明的尺寸。

The term packed array is used to refer to the dimensions declared before the data identifier name. The term unpacked array is used to refer to the dimensions declared after the data identifier name.

bit [7:0] c1; // packed array of scalar bit types
real u [7:0]; // unpacked array of real types

您已经声明了解压缩数组，因此，您不能将其分配给一个值，因此会出现错误消息。对于解压缩的数组，必须使用聚合表达式来分配整个数组：

You have declared an unpacked array, therefore you cannot assign it to a value, hence the error message. With an unpacked array you have to use an aggregate expression to assign the entire array:

logic [7:0] register_file [3:0] = {8'b0, 8'b0, 8'b0, 8'b0};

如果声明了 packed 数组，则可以将其分配为平面向量：

If you declare a packed array you can then assign as though it was a flat vector:

logic [7:0][3:0] register_file = '0;

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