如何在Verilog中为输出reg“分配"一个值? [英] How to 'assign' a value to an output reg in Verilog?

问题描述

(在此插入非常基本的问题免责声明)

( insert really basic question disclaimer here )

更具体地说，我有以下声明:

More specifically, I have the following declaration:

output reg icache_ram_rw

在代码的某些地方，我需要在这个 reg 中放置零值.这是我尝试过的方法和结果:

And in some point of the code I need to put the zero value in this reg. Here's what I've tried and the outcomes:

assign icache_ram_rw = 1'b0;
( declarative lvalue or port sink reg icache_ram_rw must be a wire )

icache_ram_rw <= 1'b0;
( instance gate/name for type "icache_ram_rw" expected - <= read )

我到底该怎么做?！

推荐答案

assign语句用于驱动wires.

如果你将某些东西声明为 reg，那么你必须在一个过程中给它赋值(always 或 initial 块).最好的做法是只在同一个 always 块中设置 reg 的值.例如:

If you've somethings declared as a reg, then you have to give it values inside a procedure ( always or initial blocks ). It's best practice to only set values of regs in the same always block. eg:

always @( * ) begin // combo logic block
   if( some_condition ) begin
      icache_ram_rw = 1'b0;
   end else begin
      icache_ram_rw = something_else;
 end

regs 和 wires 之间有重要的区别，你应该仔细阅读.

There are important differences between regs and wires that you should read up on.

我有一种感觉，如果您要驱动 RAM 信号，则需要一些时钟逻辑.在这种情况下，您将需要如下所示的代码:

I've a feeling though that you'll need some clocked logic if you're driving RAM signals. In this case, you'll need code that looks something like this:

// some parameter definitions to make logic 'read' clearer.
localparam READ = 1'b0; 
localparam WRITE = 1'b1;

// standard clocked logic 'template' that synthesis tools recognise.
always @( posedge clk or negedge resetb )
  if( !resetb ) begin  // asynchronous active low reset
     icache_ram_rw <= READ;
  end else if( some_enable_condition ) begin
     icache_ram_rw <= WRITE;
  end else begin
     icache_ram_rw <= READ;
  end

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