一个模块的输出，用作Verilog中另一个模块的输入 [英] Output of a module used as input of another in verilog

问题描述

在模块A内时，我试图将模块B的输出用作另一个模块C的输入.从本质上讲，这是一个执行"开关，在满足某些条件后，该开关会在模块B中翻转，然后执行此操作应该被认为是模块C激活的触发器.是否可以像这样链接输出和输入?

While inside a module A I'm trying to use the output of a module B as the input of another module C. Essentially this is a "go" switch that is flipped in module B after certain conditions are met and then this is supposed to be the trigger for module C to activate. Is it possible to link an output and input like this?

我一直在阅读，发现此图片特别有用-但是，我不太了解网络的概念，或者它们是否会有所帮助.将模块B的输出连接到用作模块C的输入的reg可以工作吗?谢谢.

I've been reading around and found this image particularly helpful - however, I don't quite understand the concept of nets or if they will be helpful. Would wiring the output of module B to a reg that's used as input to module C work? Thanks.

我正在寻找类似此(涉及3个不同的模块)之类的示例，模块B和模块A中的模块C.我想将B的输出连接到C的输入.

I'm looking for something like this (involving 3 different modules) where I'm instantiating a module B and a module C within a module A. I want to connect B's output to C's input.

推荐答案

您可以建立这些连接 例如:

you can make those connections For example:

module my_moduleA (inA, outA)
input inA;
output reg outA; //If you want to assign something to out inside an always block, it has to be output reg, otherwise you will have to use assign out from an always block.

//Put your logic here

endmodule

module my_moduleB (inB, outB)
input inB;
output reg outB; //If you want to assign something to out inside an always block, it has to be output reg, otherwise you will have to use assign out from an always block.

//Put your logic here

//Instantiation of module A
my_moduleA instance(  //Here is the connection made between module A and B
.inA (inB),  
.outA (outB));
endmodule

连接方式是这样的，如果要在内部信号上进行连接，则可以使用线型

This is how the connections are made, if you want to make those connections on internal signals, then you can use wire type

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