Verilog 错误:不是有效的左值 [英] Verilog error: not a valid l-value

问题描述

我正在尝试测试电线是否打开以表示我的 alu 代码中是否存在错误/溢出.鉴于此代码:

I'm trying to test if a wire(s) is on or not to signify if there is an error/overflow in my alu code. Given this code:

output reg[3:0]x;                       // line 149
output wire error;
output wire overflow;

always @* begin
    if(error || overflow) begin         
        assign x = 4'b1111;             // line 155
        assign error = ~error;
        assign overflow = ~overflow;
    end else begin
        assign x = opcode;
    end
end

我收到以下错误消息:

uut 是我的测试平台中名为 main

uut is my instantiation unit in my testbench called main

推荐答案

示例中的代码有几个问题.

The code in the example has several issues.

1) 您尝试使用程序分配"，这是一个高级 verilog 主题.换句话说，assign 语句位于 always 块内.这是不可综合的，只能用于 reg 类型，并且在非常特殊的情况下在 verilog 中存在.不要不要使用它.

1) you tried to use 'procedural assignments' which is an advanced verilog topic. In other words assign statement inside of an always block. This is not synthesizable, can only be used on reg types, and is there in verilog for very special cases. Do not use it.

您的错误消息来自 error 和 overflow 被声明为 wire.

You error messages coming from the fact that error and overflow are declared as wire.

2) 您试图在非时钟逻辑中为自身分配一个值的反转版本.它不会以您期望的方式运行.根据使用情况，它要么无法切换，要么会导致无限的零延迟循环，或者在您的情况下，它可能只会产生故障.

2) you are trying to assign inverted version of a value to itself in a non-clocked logic. It will not behave the way you expect. Depending on usage it can either not toggle or will cause an infinite zero-delay loop, or in your case it could just generate a glitch.

因此，您的代码可能应如下所示:

So, potentially, your code should look something like the following:

input wire clk; // << you need clock
output reg[3:0]x;                       // line 149
output wire error;
output wire overflow;

reg error_reg, overflow_reg; 

 always @(posedge clk) begin
    if(error || overflow) begin         
        x <= 4'b1111;             // line 155
        error_reg <= ~error;
        overflow_reg <= ~overflow;
    end else begin
        x <= opcode;
    end
 assign error = error_reg;
 assign overflow = overflow_reg;
end

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