在Verilog中使用reg类型输入 [英] inout with reg type in verilog

问题描述

我在c中使用inout，但要使c处于过程分配的LHS上，它必须是reg类型变量.有人可以帮我这个代码吗?

I have used inout with c but for c to be on the LHS of procedural assignment, it needs to be a reg type variable. Can anyone help me out with this code?

module multiedgeclk(input clk ,[7:0] a,b,d, inout [7:0] c, output reg [7:0]f); 
always @(posedge clk)
c <= a + b;
always @(negedge clk)
f = c & d;
endmodule

推荐答案

在Verilog中，inout是端口的方向. wire或reg是信号的类型. 如果要驱动双向端口，则应将其声明为inout wire或inout并使用使能信号进行驱动 这是双向端口的示例.

In verilog inout is the direction of the port. wire or reg is the type of the signal. If you want to drive a bi-directional port, it should be declare as inout wire or inout and drive it with enable signal Here is a example of bi-directional port.

module ABC( inout [7:0] c );
reg [7:0] c_out;
reg out_en;
assign c = out_en ? 8'hz : c_out; 
/* something here
... 
*/
endmodule

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