为什么我们在 FGPA/VHDL/VIVADO 中使用 REG? [英] Why do we use REG in FGPA / VHDL / VIVADO?

问题描述

我正在使用赛灵思的 vivado 进行 verilog 编程.

I am programming with Xilinx's vivado in verilog.

我想知道为什么对于某些输出我们使用 reg

I was wondering why for some outputs we use reg

例如reg [3:0] encoder_output我们使用它是因为我们的 16 到 4 编码器有 4 个输出，对吗?我假设我们在需要存储某些东西"时使用 reg

For example reg [3:0] encoder_output we use that because our 16 to 4 encoder has 4 outputs right? I am assuming that we use reg whenever we need to "STORE SOMETHING"

我的想法对吗??

推荐答案

这实际上并不是一个愚蠢的问题，尽管遭到了所有反对.在开始，设计师创建了网络和寄存器.网络旨在作为硬件元素之间的连接，并具有驱动它们的价值；他们没有持有这些价值观.网络通常声明为 wire.寄存器是数据存储元素，并且确实保存了一个值；它们通常声明为 reg.随着时间的推移，很明显这种划分(看起来像硬件")是没有意义的，并且至少有人提出了从语言中删除网络/寄存器区别的建议.这从未发生过(除非您认为 SystemVerilog 是Verilog"，我不这么认为).

It's not actually a stupid question, despite all the downvotes. In The Beginning, The Designer created nets and registers. Nets were intended as connections between hardware elements, and had values driven onto them; they didn't hold those values. Nets are normally declared as wire. Registers were data storage elements, and did hold a value; they are normally declared as reg. Over time, it became clear that this division (which sort-of-looks-like "hardware") doesn't make sense, and at least one proposal was made to drop the net/register distinction from the language. This never happened (unless you consider SystemVerilog to be 'Verilog', which I don't).

所以，您的问题在 30 年前是有道理的，而您的答案应该是正确的".

So, your question made sense 30 years ago, and your answer would have been "correct".

然而，在实践中，您使用哪个并不重要.真正的区别在于，您只能从顺序代码(always/etc)中分配给 reg，否则分配给 wire.这个要求完全是武断的，只是因为历史原因而存在.你只需要学习规则.

However, in practice, it doesn't matter which you use. The real distinction is that you can only assign to a reg from within sequential code (always/etc), and to a wire otherwise. This requirement is completely arbitrary and only exists for historical reasons. You just need to learn the rules.

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