为什么不在VHDL中使用两进程状态机? [英] Why not a two-process state machine in VHDL?
问题描述
当我学习了如何在VHDL中表达有限状态机时，它是采用两进程体系结构的.一个过程处理时钟/复位信号，另一个过程处理更新状态和输出的组合逻辑.下面是一个示例.
When I learnt how to express finite state machines in VHDL, it was with a two-process architecture. One process handles the clock/reset signals, and another handles the combinatorial logic of updating the state and output. An example is below.
我看到这种风格受到批评(请参阅评论和对例如这个问题)，但从未详细说明.我想知道这背后是否有客观原因.
I've seen this style criticised (see the comments and answer to this question for example), but never in any detail. I'd like to know whether there are objective(ish) reasons behind this.
是否有避免这种风格的技术原因?Xilinx的合成器似乎将其检测为状态机(您可以在输出中看到它，并验证转换)，但是其他人是否为它挣扎，还是生成了质量较差的实现?
Are there technical reasons to avoid this style? Xilinx' synthesiser seems to detect it as a state machine (you can see it in the output, and verify the transitions), but do others struggle with it, or generate poor quality implementations?
这不是惯用的VHDL吗?记住避免基于意见的答案；如果不是惯用的，是否有使用不同风格的广泛使用的教学资源或参考资料?习惯用法也可能存在，因为例如有些错误很容易用正确的样式捕获，或者因为代码结构可以更好地表达问题域，或者由于其他原因.
Is it just not idiomatic VHDL? Remember to avoid opinion-based answers; if it's not idiomatic, is there a widely used teaching resource or reference that uses a different style? Idiomatic styles can also exist because, eg. there are classes of mistakes that are easy to catch with the right style, or because the code structure can better express the problem domain, or for other reasons.
(请注意，我并不是要对不同样式进行定义或演示，我想知道是否存在客观原因来明确避免执行两个过程.)
(Please note that I'm not asking for a definition or demonstration of the different styles, I want to know if there are objective reasons to specifically avoid the two-process implementation.)
可以在自由范围VHDL (p89).这是一个非常简单的示例:
Some examples can be found in Free Range VHDL (p89). Here's a super simple example:
library ieee;
use ieee.std_logic_1164.all;
-- Moore state machine that transitions from IDLE to WAITING, WAITING
-- to READY, and then READY back to WAITING each time the input is
-- detected as on.
entity fsm is
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic;
output : out std_logic
);
end entity fsm;
architecture fsm_arc of fsm is
type state is (idle, waiting, ready);
signal prev_state, next_state : state;
begin
-- Synchronous/reset process: update state on clock edge and handle
-- reset action.
sync_proc: process(clk, rst)
begin
if (rst = '1') then
prev_state <= idle;
elsif (rising_edge(clk)) then
prev_state <= next_state;
end if;
end process sync_proc;
-- Combinatorial process: compute next state and output.
comb_proc: process(prev_state, input)
begin
case prev_state is
when idle =>
output <= '0';
if input = '1' then
next_state <= waiting;
else
next_state <= idle;
end if;
when waiting =>
output <= '1';
if input = '1' then
next_state <= ready;
else
next_state <= waiting;
end if;
when ready =>
output <= '0';
if input = '1' then
next_state <= waiting;
else
next_state <= ready;
end if;
end case;
end process comb_proc;
end fsm_arc;
(请注意，我目前无法使用合成器，因此其中可能存在一些错误.)
(Note that I don't have access to a synthesiser right now, so there might be some errors in it.)
推荐答案
我始终建议使用单进程状态机，因为它避免了初学者极其常见的两类基本错误:
I always recommend one-process state machines because it avoids two classes of basic errors that are exceedingly common with beginners:
- 组合过程的灵敏度列表中缺少项目会导致模拟行为异常.由于大多数合成器都不在乎灵敏度列表，因此它甚至可以在实验室中工作.
- 使用组合结果之一作为输入而不是注册版本，会导致时钟不循环或只是长路径/跳过状态.
重要的是，组合过程降低了仿真效率.
Less importantly, the combinational process reduces simulation efficiency.
客观上来说，我发现它们更易于阅读和维护；他们需要更少的样板，并且我不必使灵敏度列表与逻辑保持同步.
Less objectively, I find them easier to read and maintnain; they require less boiler plate and I don't have to keep the sensitivity list in sync with the logic.
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