VHDL 状态机差异(用于综合) [英] VHDL state machine differences (for synthesization)
问题描述
我正在上一门关于嵌入式系统设计的课程，我的一个同学上了一门课程，声称另一门课程的讲师不会让他们实现这样的状态机:
I am taking a class on embedded system design and one of my class mates, that has taken another course, claims that the lecturer of the other course would not let them implement state machines like this:
architecture behavioral of sm is
type state_t is (s1, s2, s3);
signal state : state_t;
begin
oneproc: process(Rst, Clk)
begin
if (Rst = '1') then
-- Reset
elsif (rising_edge(Clk)) then
case state is
when s1 =>
if (input = '1') then
state <= s2;
else
state <= s1;
end if;
...
...
...
end case;
end if;
end process;
end architecture;
但他们不得不这样做:
architecture behavioral of sm is
type state_t is (s1, s2, s3);
signal state, next_state : state_t;
begin
syncproc: process(Rst, Clk)
begin
if (Rst = '1') then
--Reset
elsif (rising_edge(Clk)) then
state <= next_state;
end if;
end process;
combproc: process(state)
begin
case state is
when s1 =>
if (input = '1') then
next_state <= s2;
else
next_state <= s1;
end if;
...
...
...
end case;
end process;
end architecture;
对于我这个非常缺乏经验的人来说，第一种方法看起来更简单，因为一切都是计时的，并且引入锁存器的风险更小(不是?).
To me, who is very inexperienced, the first method looks more fool proof since everything is clocked and there is less (no?) risk of introducing latches.
我的同学无法解释为什么他的讲师不让他们使用另一种实现方式，所以我试图找出每种方法的优缺点.他们中的任何一个在行业中都是首选吗?为什么我要避免其中一个?
My class mate can't give me any reason for why his lecturer would not let them use the other way of implementing it so I'm trying to find the pros and cons of each. Is any of them prefered in industry? Why would I want to avoid one or the other?
推荐答案
单进程形式更简单、更短.仅此一项就减少了它包含错误的机会.
The single process form is simpler and shorter. This alone reduces the chance that it contains errors.
然而，它也消除了困扰对方组合过程的不完整的敏感性列表"问题的事实应该使其成为明显的赢家，而不管其他任何考虑.
However the fact that it also eliminates the "incomplete sensitivity list" problem that plagues the other's combinational process should make it the clear winner regardless of any other considerations.
然而，有如此多的文本和教程提出相反的建议，没有适当地证明该建议的合理性，或者(至少在一种情况下我找不到 atm)将一个愚蠢的错误引入到单一流程表单中并拒绝整个想法那个错误的理由.
And yet there are so many texts and tutorials advising the reverse, without properly justifying that advice or (in at least one case I can't find atm) introducing a silly mistake into the single process form and rejecting the entire idea on the grounds of that mistake.
单进程形式的唯一事情(AFAIK)做得不好是非时钟输出.无论如何，这些都是 (IMO) 糟糕的做法，因为它们在最好的情况下可能是比赛，并且可以通过单独的组合过程处理仅在您确实需要的情况下用于该输出.
The only thing (AFAIK) the single-process form doesn't do well is un-clocked outputs. These are (IMO) poor practice anyway as they can be races at the best of times, and could be handled by a separate combinational process for that output only if you really had to.
我猜这背后有一些实际的原因；也许是 1990 年代中期的综合工具，它无法可靠地处理单一流程形式，并使其成为讲师从中学习的原始文档.就像那些该死的非标准 std_logic_arith 库一样.所以这个神话一直延续下去......
I'm guessing there was originally some practical reason behind it; maybe a mid-1990s synthesis tool that couldn't reliably handle the single process form, and that made it into the original documentation that the lecturers learned from. Like those blasted non-standard std_logic_arith libraries. And so the myth has been perpetuated...
如果这些讲师看到了可以通过现代综合工具传递的信息:整数、枚举、记录类型、循环、函数和程序更新信号(Xilinx ISE 现在可以接受这些内容.某些版本的 Synplicity函数有问题，但接受带有 Out 参数的相同过程).
Those same lecturers would probably have a fit if they saw what can pass through a modern synthesis tool : integers, enumerations, record types, loops, functions and procedures updating signals (Xilinx ISE is now fine with these. Some versions of Synplicity have trouble with functions, but accept an identical procedure with an Out parameter).
另一条评论:我更喜欢 if Rst = '1' then 而不是 if (Rst = '1') then.它看起来不像线路噪声(或 C).
One other comment : I prefer if Rst = '1' then over if (Rst = '1') then. It looks less like line noise (or C).
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