设计用于初始化的 VHDL 状态机 [英] Design VHDL state machine for initialization

问题描述

您如何最聪明地设计用于初始化芯片的 VHDL 状态机.

How do you smartest design a VHDL state machine for initializing a chip.

我目前的设计是(在伪代码中):

My current design is (in pseudo code):

....
....
案例状态:
当 s0 =>
VHDL_CODE_FOR_WRITING_VALUE_TO_REGISTER
状态:= s1;
当 s1 =>
VHDL_CODE_FOR_WRITING_ANOTHER_VALUE_TO_REGISTER
状态:= s1;
当 s2 =>
DO_SOMETHING_ELSE_TO_FINISH_INIT
....
....
结案；

....
....
case state:
when s0 =>
VHDL_CODE_FOR_WRITING_VALUE_TO_REGISTER
state := s1;
when s1 =>
VHDL_CODE_FOR_WRITING_ANOTHER_VALUE_TO_REGISTER
state := s1;
when s2 =>
DO_SOMETHING_ELSE_TO_FINISH_INIT
....
....
end case;

s0 和 s1 中的代码仅在写入寄存器的值上有所不同.

The code in s0 and s1 only differs by the value that is written to the register.

这让我觉得一定有更聪明的方法(仍然可以合成)?

This made me think that there must be a smarter way (which is still Synthesize able)?

让我觉得有些事情可以做得更聪明的是不要重复自己"这句话，但我不确定这是否适用于 VHDL.

What made me think something can be done more clever, is the phrase "Don't repeat yourself", but I'm not sure this applies to VHDL.

推荐答案

如果您在状态 s0 和 s1 中有共同的赋值，请将其从 case 语句中拉出.

If you have common assignments in states s0 and s1, pull it out of the case statement.

case state:
when s0 =>    
    a <= '0';
    b <= '1';
    c <= '0';
    nextState <= s1;
when s1 =>    
    a <= '0';
    b <= '1';
    c <= '1';
    nextState <= s2;
when s2 =>    
    a <= '1';
    b <= '0';
    c <= '1';
endcase;

...会变成...

a <= '0';
b <= '1';
c <= '1';

case state:
when s0 =>    
    c <= '0';
    nextState <= s1;
when s1 =>    
    nextState <= s2;
when s2 =>    
    a <= '1';
    b <= '0';
endcase;

...或者如果这不合适，将代码拉入一个函数并在每种情况下调用它.

...or if that isn't suitable, pull the code into a function and call that in each case.

虽然没有任何 VHDL 特定于此.

There's nothing VHDL specific about this though.

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