模拟器和合成器之间初始化状态机的区别 [英] Difference in initializing a state machine between a simulator and synthesizer

问题描述

我的问题是关于综合状态机中使用的第一个状态.

My question is regarding the first state used in a synthesized state machine.

我正在使用Lattice iCE40 FPGA，用于仿真的EDA Playground和用于合成的Lattice的Diamond编程器.

I'm working with a Lattice iCE40 FPGA, the EDA Playground for simulation and Lattice's Diamond Programmer for synthesizing.

在下面的示例中，我正在生成一系列信号(该示例仅显示引用状态机的行).这在模拟中效果很好；即访问的第一种情况是sm_init_lattice并生成所需的信号).但是，合成版本直接进入sm_end并停留在该位置.结果，输出信号保持低电平.

In the following example I am generating a series of signals (the example only shows the lines referring to the state machine). This works fine in simulation; i.e. the first case accessed is sm_init_lattice and the required signals are produced). However, the synthesized version goes straight to sm_end and stays there. As a result the output signal stays low.

-- state machine
type t_SM_peaks is (sm_init_lattice,
                    sm_high_start_up, sm_low_start_up, sm_peaks, sm_end);

signal r_SM_peaks : t_SM_peaks;

p_ARRAY_INTS_STDLOG_2D : process (i_Clk) is
begin
  if rising_edge(i_Clk) then
    case r_SM_peaks is
      when sm_init_lattice =>
        ...
        r_SM_peaks <= sm_high_start_up;
      when sm_high_start_up =>
        ...
        r_SM_peaks <= sm_low_start_up;  
      when sm_low_start_up =>
        ...
        r_SM_peaks <= sm_peaks;
      when sm_peaks =>
        ...
        r_SM_peaks <= sm_end;                        -- peaks completed
      when sm_end =>
        ...
        r_SM_peaks <= sm_end;
      when others =>
        r_SM_peaks <= sm_high_start_up;
    end case;
  end if;

end process p_ARRAY_INTS_STDLOG_2D;

但是，如果我进行如下更改(以"CHANGE"表示)，那么我将获得所需的信号集.

However, if I make one change as follows (indicated with 'CHANGE') then I get the set of signals that I require.

type t_SM_peaks is (sm_init_lattice,
                    sm_high_start_up, sm_low_start_up, sm_end, sm_peaks);

signal r_SM_peaks : t_SM_peaks;

p_ARRAY_INTS_STDLOG_2D : process (i_Clk) is
begin
  if rising_edge(i_Clk) then 
    case r_SM_peaks is
      when sm_init_lattice =>
        ...
        r_SM_peaks <= sm_high_start_up;
      when sm_high_start_up =>
        ...
        r_SM_peaks <= sm_low_start_up;
      when sm_low_start_up =>
        ...
        r_SM_peaks <= sm_peaks;
      when sm_peaks =>
        ...
        r_SM_peaks <= sm_end;                        -- peaks completed
      when sm_end =>
        ...
        -- CHANGE - swapped 'sm_end' for 'sm_init_lattice'
        --r_SM_peaks <= sm_end;
        r_SM_peaks <= sm_init_lattice;             
      when others =>
        r_SM_peaks <= sm_high_start_up;             
    end case;
  end if;

end process p_ARRAY_INTS_STDLOG_2D;

任何人都可以解释发生了什么吗?难道我做错了什么?如有任何建议，我将不胜感激.

Can anyone explain what is happening, please? Am I doing something wrong? I'll be grateful for any suggestions.

推荐答案

在仿真中，VHDL中的所有内容均默认为其左手值.在您的代码中，这将是sm_init_lattice，这说明了您的模拟通过的原因.

In simulation, a everything in VHDL defaults to its left hand value. In your code, that would be sm_init_lattice, which explains why your simulation passes.

但是，我没有看到复位信号.因此，在您的硬件中，存储FSM状态的触发器将重置为某些状态，但这可能不是代表sm_init_lattice状态的组合.

However, I see no reset signal. So, in your hardware, the flip-flops that store the state of your FSM will be reset to some states, but that probably isn't the combination that represents the sm_init_lattice state.

如果没有更改，则在硬件方面，FSM可能正在初始化为sm_end附近的某个状态，并且当进入该状态时，它将停留在该状态.通过进行更改，您可以允许FSM在赛道上走更多圈，因此无论初始状态如何，它都会在所有状态下前进.

Without your change, in hardware, the FSM is perhaps initialising to some state near sm_end and and when it gets into that state, it will stay there. By making your change, you are allowing the FSM to take more laps round the track, so it will progress through all the states whatever state it initially finds itself.

解决方案是实施适当的重置(异步或同步-FPGA人们似乎更喜欢同步).

The solution is to implement a proper reset (either asynchronous or synchronous - FPGA people seem to prefer synchronous).

使用枚举类型对状态机进行编码非常好，因为该代码易于阅读和维护，您无需进行任何状态编码，就可以查看波形上的状态展示.但是，使用枚举类型对状态机进行编码无法使您对统一状态进行建模，这可能是造成问题的原因.在这方面，System-Verilog优于VHDL，因为可以声明一个枚举类型，该类型也可以是未知的.

The use of enumerated types to code state machines is nice, because the code is easy to read and maintain, you don't have to commit to any state encoding and you get to see what state you're in on a waveform display. However, using enumerated types to code state machines does not enable you to model an unitialised state, which is probably the cause of your problem. System-Verilog is superior to VHDL in this respect, because it is possible to declare an enumerated type which can also be unknown.

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