尝试模拟时 Verilog 模块中未解决的参考错误 [英] Unresolved Reference Error in Verilog Module when trying to simulate
问题描述
当我尝试通过测试平台模拟以下模块时,收到此错误:
When I try to simulate the following module via a testbench, I receive this error:
未解析的对if2to4"的引用
unresolved reference to 'if2to4'
这是我的代码:
module h3to8(din, eout, en);
//Port Assignments
input [2:0] din;
input [0:0] en;
output reg [7:0] eout;
//3-to-8 decoder
always @(din)
begin
eout = 8'b00000000;
if(din[2] == 1'b0)
if2to4 half1 (din[1:0], eout[3:0], en);
else
if2to4 half2 (din[1:0], eout[7:4], en);
end
endmodule
module if2to4 (in, out, en);
//Port Assignments
input [1:0] in;
input [0:0] en;
output reg [3:0] out;
//2-to-4 decoder
always @(in)
begin
if(en == 0)
out = 4'b0000;
else
if(in == 0)
out = 1;
else if(in == 1)
out = 2;
else if(in == 2)
out = 4;
else
out = 8;
end
endmodule
verilog 代码旨在使用两个 2 对 4 解码器实现 3 对 8 解码器.我以为我正确地实例化了模块,但我一直收到有关模块 if2to4
的未解决的参考错误.代码编译没有错误,这个特定的错误只在尝试运行模拟时发生.
The verilog code is designed to implement a 3-to-8 decoder using two 2-to-4 decoders. I thought I instantiated the modules correctly, but I keep receiving an unresolved reference error in regard to module if2to4
. The code compiles without error, and this particular error only occurs when trying to run a simulation.
推荐答案
你不能在这样的 always 块中实例化模块.试试这个:
You can not instantiate modules inside an always block like that. Try this:
module h3to8(din, eout, en);
//Port Assignments
input [2:0] din;
input [0:0] en;
output reg [7:0] eout;
//3-to-8 decoder
if2to4 half1 (din[1:0], eout[3:0], en);
if2to4 half2 (din[1:0], eout[7:4], en);
endmodule
或者,您可以使用 din[2]
作为启用的一部分:
Or, you can use din[2]
as part of the enable:
module h3to8(din, eout, en);
//Port Assignments
input [2:0] din;
input [0:0] en;
output reg [7:0] eout;
//3-to-8 decoder
if2to4 half1 (din[1:0], eout[3:0], en&~din[2]);
if2to4 half2 (din[1:0], eout[7:4], en&din[2]);
endmodule
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