错误 (10170):TrafficLight.v(59) 文本“endcase"附近的 Verilog HDL 语法错误；期待“结束" [英] Error (10170): Verilog HDL syntax error at TrafficLight.v(59) near text "endcase"; expecting "end"

问题描述

我是 veriloghdl 的新手，我在 verilog hdl 中遇到此错误

I am new to veriloghdl and I am getting this error in verilog hdl

Error (10170): Verilog HDL syntax error at TrafficLight.v(59) near text "endcase";  expecting "end"

谁能告诉我出了什么问题?

Can anyone tell me what is wrong?

我的代码是

module TrafficLight(t, state, next_state, clk, out);

input t, clk;
output out;
localparam s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101;
reg[2:0] state, next_state, tt;
always@(posedge clk)
    begin
    case(state)
        3'b000:
            if(tt < 5)
                next_state = s0;
            else
                begin
                next_state = s1;
                assign out [5:0] = 6'b100001;
                end
        3'b001:
            if(tt < 1)
                next_state = s1;
            else
            begin
                next_state = s2;
                assign out [5:0] = 6'b010001;
            end
        3'b010:
            if(tt < 1)
                next_state = s2;
            else
            begin
                next_state = s3;
                assign out [5:0] = 6'b001001;
            end
        3'b011:
            if(tt < 5)
                next_state = s3;
            else
            begin
                next_state = s4;
                assign out [5:0] = 6'b001100;
            end
        3'b100:
            if(tt < 1)
                next_state = s4;
            else
            begin
                next_state = s5;
                assign out [5:0] = 6'b001010;
            end
        3'b101:
            if(tt < 1)
                next_state = s0;
            else
                begin
                next_state = s5;
                assign out [5:0] = 6'b001001;
                end
    endcase


    always@(posedge clk);
        begin
        state = next_state;
        tt = tt - 1;
        end

endmodule

我认为错误发生在 endcase 和 endmodule 行上.我想我必须用一些东西来关闭它们.

The error occured I think on the lines endcase and endmodule. I think I would have to close them with something.

推荐答案

您的代码中有几个错误 -

There are a couple of errors in your code -

您错过了endcase"语句之后的end".在 case 语句之前的 begin 块需要 end.

You missed the "end" after the "endcase" statement. The end is required for the begin block just before the case statement.

您已添加;"在始终块声明中.

You have added ";" in the always block declaration.

always@(posedge clk);
    begin
    state = next_state;
    tt = tt - 1;
    end

不需要;"在始终块中.

There is no need of an ";" in the always block.

module TrafficLight(t, state, next_state, clk, out);

input t, clk;
output out;
localparam s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101;
reg[2:0] state, next_state, tt;

在上面的代码段中，我看到您已将state"和next_state"作为端口添加到模块，但尚未为它们分配任何方向.要么将它们作为端口删除，要么将它们作为输入"或输出".

In the above snippet I see that you have added "state" and "next_state" as ports to the module but haven't assigned any direction to them. Either remove them as ports or make them as "input" or "output".

在驱动 out reg 时，您还需要删除assign"语句.由于它位于程序块内，因此这里不需要分配".

You would also need to remove the "assign" statement when driving the out reg. Since it is inside a procedural block you don't need an "assign" here.

您可以在此处

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