Verilog 循环条件 [英] Verilog Loop Condition

问题描述

我对 verilog 完全陌生，我必须很快了解我在大学学习的一门课程.所以我在玩我的 altera DE2 板和 quartis2 并学习它的来龙去脉.

I am completely new to verilog and I have to know quite a bit of it fairly soon for a course I am taking in university. So I am play around with my altera DE2 board and quartis2 and learning the ins and outs.

我正在尝试制作一个通过开关打开和关闭的计数器.到目前为止，计数器根据按键计数和重置.

I am trying to make a counter which is turned on and off by a switch. So far the counter counts and resets based on a key press.

这是我的错误:

   Error (10119): Verilog HDL Loop Statement error at my_first_counter_enable.v(19): loop with non-constant loop condition must terminate within 250 iterations

我知道我被要求提供一个循环变量，但即使这样做我也会出错.这是我的代码:

I understand I am being asked to provide a loop variable, but even doing so I get an error. This is my code:

module my_first_counter_enable(SW,CLOCK_50,LEDR,KEY);

    input CLOCK_50;
    input [17:0] SW;
    input KEY;

   output [17:0] LEDR;

   reg [32:0] count;
   wire reset_n;
   wire enable;

   assign reset_n = KEY;
   assign enable = SW[0];
   assign LEDR = count[27:24];


   always@ (posedge CLOCK_50 or negedge reset_n) begin
       while(enable) begin
           if(!reset_n)
               count = 0;
           else
               count = count + 1;
       end
    end

endmodule

我希望有人能指出我在循环中的错误并允许我继续.

I hope someone can point out my error in my loop and allow me to continue.

谢谢！

推荐答案

我认为您不想在那里使用 while 循环.怎么样:

I don't think you want to use a while loop there. How about:

   always@ (posedge CLOCK_50 or negedge reset_n) begin
           if(!reset_n)
               count <= 0;
           else if (enable)
               count <= count + 1;
    end

我还添加了非阻塞赋值<=，更适合同步逻辑.

I also added non-blocking assignments <=, which are more appropriate for synchronous logic.

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