在VHDL中设计移位寄存器 [英] Design a shift register in VHDL

问题描述

我尝试将bch代码设计为移位寄存器，所以我有以下示意图:

I try to design a bch code as a shift register, so I have this schematic:

(可点击)

然后我在Altera Quartus中制作了VHDL代码来设计带有循环的移位寄存器，编译工作正常，但是在ModelSim中进行仿真时没有得到预期的结果(无输出).我的代码中可能有一些错误:

And I made a VHDL code in Altera Quartus to design this shift register with loops, the compilation works but it doesn't make the expected result during the simulation in ModelSim (no output). It may have some errors in my code:

-- Library declaration
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;


-- Entity declaration
ENTITY bchcode_implementation_top IS

PORT(clk : IN std_logic;                    
  Q : OUT std_logic_vector(7 downto 0));

END bchcode_implementation_top;


-- Architecture declaration
ARCHITECTURE arch_bchcode_implementation_top OF bchcode_implementation_top IS

SIGNAL M: std_logic_vector(7 downto 0) := "10000000";

BEGIN
PROCESS(clk)

    VARIABLE W: std_logic;
   VARIABLE D: std_logic_vector(7 downto 0) := "00000000";

        BEGIN
            loop_bchcode: FOR I IN 7 TO 0 LOOP
                IF rising_edge(clk) THEN
                    W := D(0) XOR M(I);
                    D(7) := W;
                    D(6) := D(7);
                    D(5) := D(6);
                    D(4) := D(5);
                    D(3) := D(4) XOR W;
                    D(2) := D(3);
                    D(1) := D(2) XOR W;
                    D(0) := D(1) XOR W;
                END IF;
            Q <= D;
        END LOOP loop_bchcode;
END PROCESS;

END arch_bchcode_implementation_top;

如果有人有想法，请..谢谢您的答复.

If someone have an idea please.. thank you for your reponse.

推荐答案

根据您的代码，我认为您想设计以下原理图:

According to your code, I think you want to design the following schematic :

正如我在上面的评论中提到的那样，如果要使用变量(而不是信号)，则必须更改分配顺序.

As I mentioned in the above comment, if you want to use variables (instead of signals), you must change the order of assignments.

另外，循环范围必须为7 DOWNTO 0(而不是7 TO 0).

Also the range of loop must be 7 DOWNTO 0 (instead of 7 TO 0).

1个周期后，输出准备就绪.如果要在8个周期内进行操作，则必须使用在每个时钟上升沿递增的计数器. (而不是使用for loop)

The output is ready after 1 cycle. If you want to do the operation in 8 cycles, you must use a counter that is incremented on each clock rising edge. (instead of using for loop)

我用上述更改编辑了您的代码，并使用Modelsim 10.3对其进行了仿真.我可以在第一个时钟上升沿得到正确的结果:

I edited your code with the above changes and simulated it with Modelsim 10.3. I could get the correct result on the first clock rising edge :

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- Entity declaration
ENTITY bchcode_implementation_top IS
    PORT(
        clk : IN  std_logic;                    
        Q   : OUT std_logic_vector(7 DOWNTO 0)
    );
END bchcode_implementation_top;


-- Architecture declaration
ARCHITECTURE arch_bchcode_implementation_top OF bchcode_implementation_top IS
    SIGNAL M : std_logic_vector(7 DOWNTO 0) := "10000000";
BEGIN

    PROCESS(clk)
        VARIABLE I : integer;
        VARIABLE W : std_logic;
        VARIABLE D : std_logic_vector(7 DOWNTO 0) := "00000000";
    BEGIN
        loop_bchcode: FOR I IN 7 DOWNTO 0 LOOP
            IF rising_edge(clk) THEN
                    W := D(0) XOR M(I);
                    D(0) := D(1) XOR W;
                    D(1) := D(2) XOR W;
                    D(2) := D(3);
                    D(3) := D(4) XOR W;
                    D(4) := D(5);
                    D(5) := D(6);
                    D(6) := D(7);
                    D(7) := W;
            END IF;
        END LOOP loop_bchcode;
        Q <= D;
    END PROCESS;

END arch_bchcode_implementation_top;

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