通过命令行附加到GNU make变量 [英] Append to GNU make variables via command line

问题描述

我正在使用GNU-make Makefile构建具有多个目标(all，clean和一些特定于项目的目标)的C项目.在调试过程中，我想在不永久编辑Makefile的情况下将一些标志附加到单个构建中(例如，添加调试符号或设置预处理器标志).

I am using a GNU-make Makefile to build a C project with several targets (all, clean, and a few project specific targets). In the process of debugging, I would like to append some flags to a single build without permanently editing the Makefile (e.g. add debugging symbols or set a preprocessor flag).

过去，我已按照以下步骤进行操作(使用调试符号示例):

In the past, I have done that as follows (using the debugging symbols example):

make target CFLAGS+=-g

不幸的是，这不是附加到CFLAGS变量上，而是清除它并停止对其进行编译.是否有一种干净的方法可以执行此操作而无需定义附加到CFLAGS和LDFLAGS末尾的某种虚拟变量?

Unfortunately, this is not appending to the CFLAGS variable, but instead, clearing it and stopping it from compiling. Is there a clean way of doing this without defining some sort of dummy variable appended to the end of CFLAGS and LDFLAGS?

推荐答案

查看覆盖指令.您可能需要修改一次makefile，但它应该执行您想要的操作.

Check out the override directive. You will probably need to modify the makefile once, but it should do what you want.

示例生成文件:

override CFLAGS += -Wall

app: main.c
    gcc $(CFLAGS) -o app main.c 

示例命令行:

$ make
gcc -Wall -o app main.c 
$ make CFLAGS=-g
gcc -g -Wall -o app main.c 

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