从make命令行触发C源代码#define [英] Triggering C source #define from`make` command line

问题描述

我想将C源代码#define链接"到makefile变量-以便能够通过make进行定义或取消定义.

I'd like to "link" a C source #define to a makefile variable - to be able to define or undefine via make.

例如

// my C source file
#ifdef SOMETHING
   // do something
#else
   // do something else
#endif 

然后SOMETHING将通过make命令行触发:

Then SOMETHING would be triggered from the make command line:

make something=true

这适用于我的makefile:

ifeq ($(something),true)
    COMPILER_FLAGS += -DSOMETHING   
endif

我在流浪，这是正确的方法吗?
有没有更简单或更完善的解决方案?

I am wandering, is this the proper way?
Is there an easier or better solution?

推荐答案

以下不是临时解决方案，但它要求您使用Make库:

The following is not an ad-hoc solution but it requires you to use a make library: gmtt is the GNUmake table toolkit and was designed more or less with such a use case in mind. You can specify tables which you access with a (modest) form of the select statement known from a relational database. This way you escape convoluted ifeq hierarchies and can introduce build parameters rather easily. Of course one can argue that in my example three very simple ifeq paragraphs would have done also, without introducing a make library, but the advantage of the below solution is that tables force you to a separation of concerns and you don't need to worry that someone has sneaked in an addtional functionality in one of the ifeq's aside from generating #define's.

include gmtt/gmtt.mk

#define a 3-column table; there must be no empty cells (put in a comment)!
define project-defs =
3
type-1   APPLES   15
type-1   ORANGES  0
type-1   PEARS   /*empty*/

type-2   APPLES   0
type-2   ORANGES  15
type-2   PEARS   /*empty*/

type-3   APPLES   15
type-3   ORANGES  15
endef

#select column 2 and 3 of the above table and create a C-source line with '#define' from them
define project-defines :=
$(call map-select,2 3,$(project-defs),$$(call str-eq,$$1,$(project-type)),\#define $$1 $$2$$(newline))
endef

$(info Building with the following defines: $(project-defines))

$(file > project_def.h,$(project-defines))

现在，使用此makefile，您可以调用make project-type=type-1，依此类推，makefile将为您生成project_def.h，它将用作普通头文件，而不是命令行中的不可见定义.

With this makefile you now can invoke make project-type=type-1 and so on and the makefile will generate for you project_def.h which will serve as a normal header file instead of invisible defines in the command line.

这篇关于从make命令行触发C源代码#define的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！