为具有多个依赖关系的单个目标编写Makefile规则 [英] Writing a Makefile rule, for a SINGLE target with MULTIPLE dependacies

问题描述

例如，如果我要用硬件描述语言编译一堆文件，则可以通过以下方式编写Makefile

For Eg., if I were to compile bunch of files in a hardware description language, I can write a Makefile in the following way

    analyze: a.v b.v c.v top.v
        vcs $(OPTIONS) a.v
        vcs $(OPTIONS) b.v
        vcs $(OPTIONS) c.v
        vcs $(OPTIONS) top.v

进行分析，将编译其依赖项中的所有文件&构建最终的可执行文件.我该如何编写一个单个Makefile规则"，它将编译其所有依赖项并构建一个可执行文件-使用类似于以下规则的方法模仿上述内容:

Make analyze, will compile all the files in its dependency & builds the final executable. How can I write a "SINGLE Makefile rule", which will compile all its dependencies and build an executable - Mimicking the above with a rule SOMETHING LIKE:

    analyze: %.v
        vcs $(OPTIONS) %.v

以上适用于单个文件依赖项.但是，如果我有多个文件依赖项，我将如何处理多个文件?我可以对所有依赖项使用"for循环"吗?我一直在寻找Makefile选项来访问要在for循环中使用的依赖文件"，但可能找不到.

The above works for a single file dependency. But, if I have multiple file dependencies how will I handle the multiples files ? Can I use a "for loop" for all the dependencies. I was looking for Makefile options to access the "dependency files" to be used in a for loop, but COULD NOT find one.

推荐答案

为每个要分析的文件使用一个虚拟图章目标:

Use a dummy stamp target for each to-be-analyzed file:

analyze : a.analyzed-stamp b.analyzed-stamp c.analyzed-stamp top.analyzed-stamp

%.analyzed-stamp : %.v
    vcs $(OPTIONS) $<
    touch $@

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