Makefile和计算出的变量名 [英] Makefile and computed variable names

问题描述

我得到了以下带有几个编译器的Makefile，我想通过变量cc在循环中调用它们:

I got the following Makefile with several compilers, and I would like to invoke them in a loop through the variable cc:

cc_x64=x86_64-linux-gnu-gcc
cc_mips=mips-linux-gnu-gcc

all:
    for arch in "x64" "mips" ; do\
    cc="cc_$$arch";\
    $($(cc)) some_file -o some_bin

通过$($(cc))，我尝试用cc_xxx替换$(cc)，然后用我尝试执行的实际命令替换它.在GNU Make的文档中，这称为计算变量名称: https://www.gnu.org/software/make/manual/html_node/Computed-Names.html

By $($(cc)), I am trying to substitute $(cc) with cc_xxx, and in turn, substitute it with the actual command I am trying to execute. This is called a computed variable name in GNU Make's documentation: https://www.gnu.org/software/make/manual/html_node/Computed-Names.html

由于某种原因，我无法使它正常工作.我想念什么?

For some reason, I cannot get this to work. What am I missing ?

推荐答案

如果我不得不使用循环，我会这样做:

If I felt compelled to use a loop, I'd do it like this:

COMPS = x86_64-linux-gnu-gcc mips-linux-gnu-gcc

all:
    for comp in $(COMPS); do\
  $$comp some_file -o some_bin; \
  done

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