Makefile通用二进制编译 [英] Makefile generic binaries compilations

问题描述

我有一组共享相同Makefile规则模式的源文件:

I have a set of source files that share the same Makefile rule pattern:

bin1: bin1.o libfoo.a
    $(LDENV) $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^

bin2: bin2.o libfoo.a
    $(LDENV) $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^

bin3: bin3.o libfoo.a
    $(LDENV) $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^

...

现在，我该如何重构它以避免一遍又一遍地重复相同的规则?如果将文件扩展名添加到二进制文件中，这很容易:

Now, how may I refactor this to avoid repeating the same rule over and over? This is easy if a file extension is added to the binaries:

%.out: %.o libfoo.a
    $(LDENV) $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^

但是可以不使用一个做同样的事情吗?

But is it possible to do the same without using one?

推荐答案

您可以使用静态模式规则:

bin1 bin2 bin3: %: %.o libfoo.a
    $(LDENV) $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^

这样更干净，您可以确定%仅匹配bin1，bin2和bin3目标(我想这是您想要的).

This way this is cleaner and you are sure that the % only match bin1, bin2 and bin3 targets (I think this is want you want).

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