每个内核都有自己的专用寄存器集吗? [英] Does each core has its own private set of registers?

问题描述

从此intel核心i7 nehalem微体系结构看

Looking from this intel core i7 nehalem microarchitecure

似乎每个内核都有其自己的私有Register文件.所以我有几个简短的问题，因为我认为只有一套寄存器不依赖于内核数.

It seems that each core has it's own private Register file. So I have a couple of short questions, because I thought that there is only 1 set of registers not dependent on number of cores.

• 每个内核都有自己的专用寄存器集吗? (rax，rbx，rsp等.)
• 每个核心都有自己的MMU和TLB吗?不仅所有内核都共享一个内核?

我知道这些问题在很大程度上取决于微体系结构，但是我认为现代x64 intel cpu的大多数遵循相同的设计原则.

I know the questions are highly microarchitecture dependent but I think majority of modern x64 intel cpu's follow the same design principle.

推荐答案

每个内核都有自己的一组寄存器，MMU，TLB，1级缓存(数据和指令)，2级缓存(这取决于处理器)等.通过"QPI"在各个内核之间支持缓存一致性，在高端Core 7和基于服务器的处理器(例如Xeon)的情况下，通过在处理器的外部引脚上暴露"QPI"，可以在多处理器母板上的所有处理器之间支持缓存一致性.这些处理器(对于不支持多处理器高速缓存一致性的处理器，"QPI"未公开".)

Each core has its own set of registers, MMU, TLB, level 1 caches (data and instruction), level 2 cache (this depends on processor) etc. Cache Coherency is supported across cores via "QPI" and in the case of high end Core 7 and server-based processors like Xeon, Cache Coherency is supported across processors on a multi-processor mother board by exposing "QPI" on the external pins of those processors (for processors where multi-processor cache coherency is not supported, "QPI" is not "exposed").

Wiki文章: Nehalem

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