确定内存位置是否在CPU缓存中 [英] Determine whether memory location is in CPU cache

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问题描述

操作系统可以确定内存页面是在DRAM中还是在交换中;例如,只需尝试访问它,如果发生页面错误,则不会.

It is possible for an operating system to determine whether a page of memory is in DRAM or in swap; for example, simply try to access it and if a page fault occurs, it wasn't.

但是,CPU缓存是否可以实现相同的功能?

However, is the same thing possible with CPU cache?

是否有任何有效的方法来判断给定的内存位置是否已加载到高速缓存行中,或知道何时加载?

Is there any efficient way to tell whether a given memory location has been loaded into a cache line, or to know when it does so?

推荐答案

通常,我认为这是不可能的.它适用于DRAM和页面文件,因为它是OS托管的资源,缓存由CPU本身管理.

In general, I don't think this is possible. It works for DRAM and the pagefile since that is an OS managed resource, cache is managed by the CPU itself.

操作系统可以对内存读取进行严格的定时循环,并尝试查看它是否足够快地完成以放入缓存中,或者是否必须进入主内存-这很容易出错.

The OS could do a tight timing loop of a memory read and try to see if it completes fast enough to be in the cache or if it had to go out to main memory - this would be very error prone.

在多核/多进程系统上,使用了缓存一致性协议在处理器之间确定它们何时需要使彼此的缓存无效时,我想您可以拥有一个定制设备,该设备可以监听操作系统要查询的该协议.

On multi-core/multi-proc systems, there are cache coherency protocols that are used between processors to determine when to they need to invalidate each other's caches, I suppose you could have a custom device that would snoop this protocol that the OS would query.

您想做什么?如果要将某些内容强制放入内存,当前的x86处理器支持以非阻塞方式将内存预取到缓存中,例如,使用Visual C ++,您可以使用

What are you trying to do? If you want to force something into memory, current x86 processors support prefetching memory into the cache in a non-blocking way, for instance with Visual C++ you could use _mm_prefetch to fetch a line into the cache.

我自己尚未完成此操作,因此使用时需您自担风险.要确定用于分析的高速缓存未命中,您可以使用某些特定于体系结构的寄存器. http://download.intel.com/design/processor/manuals/253669.pdf ,附录A给出了性能调整事件".这不能用于确定单个地址是在缓存中还是何时在缓存中加载,但是可以用于整体统计信息.我相信这就是vTune(此级别的非凡的探查器)所使用的.

I haven't done this myself, so use at your own risk. To determine cache misses for profiling, you may be able to use some architecture-specific registers. http://download.intel.com/design/processor/manuals/253669.pdf, Appendix A gives "Performance Tuning Events". This can't be used to determine if an individual address is in the cache or when it is loaded in the cache, but can be used for overall stats. I believe this is what vTune (a phenomenal profiler for this level) uses.

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