L4缓存发生了什么? [英] What happened to the L4 cache?

问题描述

关于L4缓存的信息并不多，但据我所知，它已用于第四代和第五代Intel处理器(2013-2014年)，但已不再是当前一代. /p>

L4不好，无效还是什么?

解决方案

对于Haswell和Broadwell，eDRAM L4缓存标签驻留在片上L3缓存中.尽管此设置简化了LLC设计，并允许更早地进行标签检查以检查是否从处理器获取数据，但由于必须将这些内存请求转发至片上L3，因此使从其他设备(例如，通过PCIe的独立GPU)访问eDRAM LLC的速度变慢.首先由LLC处理.为了解决这个问题，eDRAM已移至Skylake中DRAM控制器上的位置(更像是内存端缓冲区，而不是缓存)

参考文献:Li，Ang等. 探索和分析现代封装内存对HPC科学内核的实际影响."高性能计算，网络，存储和分析国际会议论文集. ACM，2017年

您可以在下面看到Broadwell，Haswell和Skylake架构. Broadwell和Haswell

蓝天

There isn't a lot of information about the L4 cache, but as far as I know, it was used in the 4th and 5th generation of Intel processors(2013-2014), but it's gone from the current generation.

Was the L4 bad, ineffective or something?

解决方案

For Haswell and Broadwell, eDRAM L4 cache tags are resident in the on-chip L3 cache. Although this setup simplifies the LLC design and allows earlier tag checking for fetches from the processor, it makes the accessing to eDRAM LLC from other devices (e.g., independent GPUs via PCIe) slower as these memory requests have to be forwarded to on-chip L3 first before being handled by the LLC. To address this, eDRAM has been moved to the position upon DRAM controllers in Skylake (more like a memory-side buffer rather than a cache)

Reference : Li, Ang, et al. "Exploring and analyzing the real impact of modern on-package memory on HPC scientific kernels." Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis. ACM, 2017

You can see Broadwell, Haswell, and Skylake architectures below. Broadwell and Haswell

Skylake

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