端口大小与连接大小不匹配 [英] port size does not match connection size
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问题描述
我有此代码:
Alu.v
module ALU(
src1_i,
src2_i,
src3_i,
src4_i,
ctrl_i,
result_o,
zero_o
);
//I/O ports
input [32-1:0] src1_i;
input [32-1:0] src2_i;
input [4-1:0] src3_i;//shmat is 5 bits instruction[10:6]
input [15-1:0] src4_i;//ori have to deal with 'zero-extended' number
input [4-1:0] ctrl_i;
output [32-1:0] result_o;
output zero_o;
//Internal signals
reg [32-1:0] result_o;
wire zero_o;
//Parameter
assign zero_o = (result_o == 0);
//Main function
always @(*) begin
case(ctrl_i)
0 :result_o <= src1_i & src2_i;//and
1 :result_o <= src1_i | src2_i;//or
2 :result_o <= src1_i + src2_i;//add
6 :result_o <= src1_i - src2_i;//substract
7 :result_o <= src1_i < src2_i ? 1 : 0;//set less than
10:result_o <= ~(src1_i - src2_i);//not the result for bne
11:result_o <= (src1_i | {16'b0000000000000000, src4_i});//ori
12:result_o <= ~(src1_i | src2_i);//nor
13:result_o <= src2_i << 16;//lui
14:result_o <= src2_i << src1_i;//sllv
15:result_o <= src2_i << src3_i;//sll
default:result_o <= 0;//default
endcase
end
endmodule
在另一个模块中:
Simple_Single_CPU.v .....
Simple_Single_CPU.v .....
ALU ALU(
.src1_i(RSdata_o),
.src2_i(reg_mux_data_o),
.src3_i(instr_o[10:6]),
.src4_i(instr_o[15:0]),
.ctrl_i(ALUCtrl_o),
.result_o(result_o),
.zero_o(zero_o)
);
我检查了端口大小和连接端口大小是否正确,但这会给我这些警告:
I have checked that the port size and connection port size is right, but it gives me these warnings:
# ** Warning: (vsim-3015) C:/Users/lypan/Downloads/Lab2/Lab2/code/Simple_Single_CPU.v(116): [PCDPC] - Port size (4 or 4) does not match connection size (5) for port 'src3_i'. The port definition is at: C:/Users/lypan/Downloads/Lab2/Lab2/code/ALU.v(15).
#
# Region: /TestBench/cpu/ALU
# ** Warning: (vsim-3015) C:/Users/lypan/Downloads/Lab2/Lab2/code/Simple_Single_CPU.v(116): [PCDPC] - Port size (15 or 15) does not match connection size (16) for port 'src4_i'. The port definition is at: C:/Users/lypan/Downloads/Lab2/Lab2/code/ALU.v(16).
#
# Region: /TestBench/cpu/ALU
如何解决警告?
推荐答案
警告是正确的.
在模块ALU
中,您具有以下声明:
In module ALU
, you have this declaration:
input [4-1:0] src3_i;//shmat is 5 bits instruction[10:6]
这将src3_i
的宽度设置为4,因为4-1 = 3,而3:0是4位.
This sets the width of src3_i
to 4 because 4-1=3, and 3:0 is 4 bits.
但是,在Simple_Single_CPU.v
中,您有:
.src3_i(instr_o[10:6]),
这会将5位信号(instr_o [10:6])连接到4位端口(src3_i).
This connects a 5-bit signal (instr_o[10:6]) to a 4-bit port (src3_i).
您必须确定信号是真正的4位还是5位.例如,如果要5位,请使用:
You must decide whether the signal should really be 4 bits or 5 bits. For example, if you want 5 bits, use:
input [5-1:0] src3_i;//shmat is 5 bits instruction[10:6]
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