如何在两个Verilog模块之间传递数组结构 [英] How to pass array structure between two verilog modules

问题描述

我正在尝试在两个模块之间传递作为reg [0:31] instructionmem [0:31]的数组结构.

I am trying to pass a array structure as reg [0:31]instructionmem[0:31] between two modules.

我将其编码如下:

模块1:

       module module1(instructionmem);
            output reg [0:31]instructionmem[0:31];
            ------------------
            ----lines of code---

            ---------------
       endmodule 

模块2:

         module module2(instructionmem);
           input [0:31]instructionmem[0:31];
           --------------------------------
           -----line of code---------------
           -------------------------------
           endmodule

测试台:

     module test_bench();
     wire [0:31]instructionmem[0:31];

     module1 m1(instructionmem);
     module2 m2(instructionmem);
     endmodule

我在此实现中遇到错误.那么我们如何发送这样的数组结构呢?

I am getting errors for this implementation. So how can we send such array structures ?

推荐答案

在Verilog中是不可能的. (请参阅Verilog 2005标准文档的第12.3.3节，语法12-4，IEEE标准1364-2005.)

This is not possible in Verilog. (See sec. 12.3.3, Syntax 12-4 of the Verilog 2005 standard document, IEEE Std. 1364-2005.)

相反，您应该展平"数组并将其作为简单向量传递，例如:

Instead you should "flatten" the array and pass it as a simple vector, e.g.:

module module1(instructionmem);
  output [32*32-1:0] instructionmem;
  reg [31:0] instructionmem_array [31:0];

  genvar i;
  generate for (i = 0; i < 32; i = i+1) begin:instmem
    assign instructionmem[32*i +: 32] = instructionmem_array[i]; 
  end endgenerate
endmodule

module module2(instructionmem);
  input [32*32-1:0] instructionmem;
  reg [31:0] instructionmem_array [31:0];

  integer i;
  always @*
    for (i = 0; i < 32; i = i+1)
      instructionmem_array[i] = instructionmem[32*i +: 32];
endmodule

module test_bench(instructionmem);
  output [32*32-1:0] instructionmem;
  module1 m1(instructionmem);
  module2 m2(instructionmem);
endmodule

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