使用来自其他两个模块的输出 (Verilog) [英] Using Outputs From Two Other Module (Verilog)

问题描述

我有一个简单的问题.

如何在一个新模块中使用其他两个模块的输出?

How can I use the outputs of two other modules with a new module?

示例:

module test1(ans, X, Y)
  output ans;
  input X, Y;

  do stuff

endmodule

module test2(ans2, X, Y)
  output ans2;
  input X, Y;

  do stuff

endmodule

module result(final_ans, ans, ans2)   <------- this is what I mean.

  do stuff

endmodule

我该怎么做?我如何调用另外两个模块?

How would I go about this? How do I call the other two modules?

感谢您的帮助.

推荐答案

您不必调用模块.您实例模块.Verilog 不像普通的编程语言，它是一种硬件模拟语言.如果您坚持使用该语言的一个子集并以正确的方式使用它，该语言也可以转换为真正的硬件.后者称为 RTL(寄存器传输语言).我强烈建议您找到一些现有的 Verilog 代码示例并研究人们如何使用它.

You do not call modules. You instance modules. Verilog is not like normal programming languages, it is a hardware simulation language. If you stick to a subset of the language and you use that in the right way that language can also be converted to real hardware. That latter is called RTL (Register Transfer Language). I strongly suggest you find some existing Verilog code examples and study how people use it.

因此，您要做的是为每个模块创建一个实例并连接输入和输出的信号.将其与将 IC 放在板上并焊接导线进行比较.但后来都在软件中.

Thus what you do is you make an instance of each module and you connect signals to the inputs and outputs. Compare it to placing an IC on a board and soldering wires to it. But then all in software.

test1 instance_of_test1 (
   .X(signal_into_X),
   .Y(signal_into_Y),
   .ans(signal_outof_ans)
);

然后您可以使用来自 test1 和 test2 的信号进入结果:

Then you can use the signals coming out of test1 and test2 to go into result:

result instance_of_result  (
   .ans(signal_outof_ans),
   .ans2(signal_outof_ans2),
   .final_ans(signal_outof_final_ans)
);

作为旁注:
我使用的示例还表明，使用端口方向的命名约定通常是一个坏主意.信号从一个模块输出并进入另一个模块.因此，名称​​signal_outof_ans对于模块test1来说很好，但对于模块result来说是错误的，因为它进入 模块.在这里，我想强调在模块 test1 级别发生的事情.(我也知道有些公司甚至将其规定为首选的编码风格，所以我正在等待对此进行抨击).在我自己的代码中，我永远不会使用它.所以这里是正确的编码方式:

Just as a side note:
The example I use also shows that naming conventions using the port direction is general a bad idea. Signals come out of one module and go into another. Thus the name signal_outof_ans is fine for the module test1 but it is wrong for the module result as there it goes into the module. Here I wanted to emphasize what happens at the level of module test1. (I also know that some companies even prescribe it as the preferred coding style so I am waiting for the flak to arrive on this). In my own code I would never use this. So here is the correct way to code:

wire ans,ans2;
test1 instance_of_test1 (
   .X(X),
   .Y(Y),
   .ans(ans)
);
...
...
result instance_of_result  (
   .ans(ans),
   .ans2(ans2),
   .final_ans(final_ans)
);

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