原子引用对共享的不可变数据进行计数是否需要内存屏障? [英] Are memory barriers necessary for atomic reference counting shared immutable data?

问题描述

我想使用引用计数来管理一些不变的数据结构，并在SMP系统上的线程之间共享它们.

I have some immutable data structures that I would like to manage using reference counts, sharing them across threads on an SMP system.

以下是发布代码的样子:

Here's what the release code looks like:

void avocado_release(struct avocado *p)
{
    if (atomic_dec(p->refcount) == 0) {
        free(p->pit);
        free(p->juicy_innards);
        free(p);
    }
}

atomic_dec是否需要内存屏障?如果是这样，什么样的内存障碍?

Does atomic_dec need a memory barrier in it? If so, what kind of memory barrier?

其他说明:该应用程序必须在PowerPC和x86上运行，因此欢迎使用任何特定于处理器的信息.我已经了解了GCC原子内建函数.至于不变性，引用计数是随对象持续时间变化的 only 字段.

Additional notes: The application must run on PowerPC and x86, so any processor-specific information is welcomed. I already know about the GCC atomic builtins. As for immutability, the refcount is the only field that changes over the duration of the object.

推荐答案

在x86上，它将变成带有锁前缀的汇编指令，例如LOCK XADD.
作为一条指令，它是不间断的.作为附加的特征"，锁定前缀会导致完整的内存屏障:

On x86, it will turn into a lock prefixed assembly instruction, like LOCK XADD.
Being a single instruction, it is non-interruptible. As an added "feauture", the lock prefix results in a full memory barrier:

"...已锁定的操作将所有未完成的加载和存储操作序列化(即，等待它们完成)." ……锁定操作相对于所有其他内存操作和所有外部可见事件都是原子性的.只有指令获取和页表访问才能传递锁定指令.锁定指令可用于同步一个处理器写入的数据和另一处理器读取的数据." -英特尔®64和IA-32架构软件开发人员手册，本章8.1.2.

"...locked operations serialize all outstanding load and store operations (that is, wait for them to complete)." ..."Locked operations are atomic with respect to all other memory operations and all externally visible events. Only instruction fetch and page table accesses can pass locked instructions. Locked instructions can be used to synchronize data written by one processor and read by another processor." - Intel® 64 and IA-32 Architectures Software Developer’s Manual, Chapter 8.1.2.

在两个

A memory barrier is in fact implemented as a dummy LOCK OR or LOCK AND in both the .NET and the JAVA JIT on x86/x64.
So you have a full fence on x86 as an added bonus, whether you like it or not. :)

在PPC上，情况有所不同.一个 LL/SC 对- _{在PPC上，可以发出} (lw)sync 指令.

On PPC, it is different. An LL/SC pair - lwarx & stwcx - with a subtraction inside can be used to load the memory operand into a register, subtract one, then either write it back if there was no other store to the target location, or retry the whole loop if there was. An LL/SC can be interrupted.
It also does not mean an automatic full fence.
This does not however compromise the atomicity of the counter in any way.
It just means that in the x86 case, you happen to get a fence as well, "for free".
_{On PPC, one can insert a full fence by emitting a (lw)sync instruction.}

总而言之，原子计数器正常工作并不需要显式的内存屏障.

All in all, explicit memory barriers are not necessary for the atomic counter to work properly.

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