x86页表如何工作? [英] How do x86 page tables work?

问题描述

我熟悉MIPS架构，该架构具有软件管理的TLB.因此，您(操作系统)要如何以及在何处存储页表和页表条目完全取决于您.例如，我做了一个有单个倒排页表的项目.我看到其他人在每个进程中使用2级页表.

I'm familiar with the MIPS architecture, which is has a software-managed TLB. So how and where you (the operating system) wants to store the page tables and the page table entries is completely up to you. For example I did a project with a single inverted page table; I saw others using 2-level page tables per process.

但是x86的故事是什么?据我了解，TLB是由硬件管理的. x86会基本告诉您:嘿，这是您当前正在使用的页表条目需要进入的[物理地址范围]"吗?但是，等等，我一直认为x86使用多级页表，因此它会告诉您将第一级放在什么位置吗?我很困惑.

But what's the story with x86? From what I know the TLB is hardware-managed. Does x86 tell basically tell you, "Hey this is where the page table entries you're currently using need to go [physical address range]"? But wait, I've always thought x86 uses multi-level page tables, so would it tell you where to put the 1st level or something...? I'm confused.

感谢您的帮助.

推荐答案

进入保护模式后，CR3寄存器指向页面目录"(您可以在进入保护模式之前将其放置在任何位置)，这是一个内存页面(请记住，小"页面为4 KiB，而大"页面为4 MiB)具有1024个指向页面表"的页面目录项(PDE).每个条目都是指针的高10位(页表的地址)，以及构成指针底部的一堆标志(呈现，允许，脏等).

Upon entering protected mode, the CR3 register points to a "page directory" (you can put it anywhere you want before you enter protected mode), which is a page of memory (remember, a "small" page is 4 KiB, and a "large" page is 4 MiB) with 1024 page directory entries (PDEs) that point to to "page tables". Each entry is the top 10 bits of a pointer (the address of the page table), plus a bunch of flags that make up the bottom portion of the pointer (present, permission, dirty, etc.).

(1024仅来自页面为4096字节而指针为4字节的事实.)

(The 1024 just comes from the fact that a page is 4096 bytes and a pointer is 4 bytes.)

每个页表"本身就是1024个页表条目"(PTE)，其中又包含1024个指向内存中的物理页的条目，以及一堆(几乎是相同)标志.

Each "page table" is itself 1024 "page table entries" (PTEs), which, again, contains 1024 entries that point to physical pages in memory, along with a bunch of (almost the same) flags.

因此，要转换32位虚拟地址，请将指针的前10位作为索引插入CR3的表中(因为有2 ¹⁰ 项)，并且-如果该PDE被进一步细分(这意味着它不是一个大"页面，您可以从标志中找出来)–您使用PDE的前20位，在该地址查找页面表，并进行索引虚拟地址的 next -最前10位输入到其中.然后，假设最低的12位告诉您实际存在的物理页面，那么最上面的20位将使您进入物理页面.

So, to translate a 32-bit virtual address, you take the top 10 bits of the pointer as an index into the table at CR3 (since there are 2¹⁰ entries), and -- if that PDE is further subdivided (meaning it isn't a "large" page, which you can figure out from the flags) -- you take the top 20 bits of the PDE, look up the page table at that address, and index into it with the virtual address's next-topmost 10 bits. Then the topmost 20 bits refer you to the physical page, assuming the bottom 12 bits tell you the physical page is actually present.

如果您使用的是物理地址扩展名(PAE)，则然后，您会得到另一个层次结构中的最顶层.

If you're using Physical Address Extension (PAE), then you get another level in the hierarchy at the very top.

注意:出于您自己的理智(也许是CPU)的考虑，您可能希望将页面目录和页面表映射到它们自己，否则事情会很快变得混乱. :)

Note: for your own sanity (and maybe the CPU's), you'd probably want to map the page directory and the page table to themselves, otherwise things get confusing fast. :)

TLB是硬件管理的-因此页表的缓存是透明的-但是有一条指令InvlPG为您使TLB中的PTE无效. (我不知道什么时候应该使用它，什么时候不应该使用.)

The TLB is hardware-managed -- so the caching of the page tables is transparent -- but there is an instruction, InvlPG, that invalidates a PTE in the the TLB for you. (I don't know exactly when you should use it and when you shouldn't.)

来源: http://wiki.osdev.org/Paging

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