x86 页表是如何工作的? [英] How do x86 page tables work?

问题描述

我熟悉 MIPS 架构，它有一个软件管理的 TLB.因此，您(操作系统)想要存储页表和页表条目的方式和位置完全取决于您.例如，我做了一个带有单个倒置页表的项目；我看到其他人在每个进程中使用 2 级页表.

I'm familiar with the MIPS architecture, which is has a software-managed TLB. So how and where you (the operating system) wants to store the page tables and the page table entries is completely up to you. For example I did a project with a single inverted page table; I saw others using 2-level page tables per process.

但是 x86 的故事是什么?据我所知，TLB 是硬件管理的.x86 是否告诉您，嘿，这是您当前使用的页表条目需要去的地方 [物理地址范围]"?但是等等，我一直认为 x86 使用多级页表，所以它会告诉你在哪里放置第一级或其他什么...?我很困惑.

But what's the story with x86? From what I know the TLB is hardware-managed. Does x86 tell basically tell you, "Hey this is where the page table entries you're currently using need to go [physical address range]"? But wait, I've always thought x86 uses multi-level page tables, so would it tell you where to put the 1st level or something...? I'm confused.

感谢您的帮助.

推荐答案

进入保护模式后，CR3寄存器指向一个页面目录"(进入保护模式前你可以放任何地方)，这是一个内存页(请记住，小"页为 4 KiB，大"页为 4 MiB)，包含 1024 个指向页表"的页目录条目 (PDE).每个条目是指针的前 10 位(页表的地址)，加上构成指针底部部分的一堆标志(存在、权限、脏等).

Upon entering protected mode, the CR3 register points to a "page directory" (you can put it anywhere you want before you enter protected mode), which is a page of memory (remember, a "small" page is 4 KiB, and a "large" page is 4 MiB) with 1024 page directory entries (PDEs) that point to to "page tables". Each entry is the top 10 bits of a pointer (the address of the page table), plus a bunch of flags that make up the bottom portion of the pointer (present, permission, dirty, etc.).

(1024只是来自页面是4096字节，指针是4字节的事实.)

(The 1024 just comes from the fact that a page is 4096 bytes and a pointer is 4 bytes.)

每个页表"本身就是 1024 个页表条目"(PTE)，其中又包含 1024 个指向内存中物理页的条目，以及一堆(几乎相同)标志.

Each "page table" is itself 1024 "page table entries" (PTEs), which, again, contains 1024 entries that point to physical pages in memory, along with a bunch of (almost the same) flags.

因此，要转换 32 位虚拟地址，您需要将指针的前 10 位作为 CR3 表中的索引(因为有 2¹⁰ 个条目)，并且 --如果该 PDE 被进一步细分(这意味着它不是一个大"页面，您可以从标志中找出) - 您获取 PDE 的前 20 位，查找该地址处的页表，并索引使用虚拟地址的 next-topmost 10 位进入它.然后最高 20 位指向物理页面，假设最低 12 位告诉您实际存在物理页面.

So, to translate a 32-bit virtual address, you take the top 10 bits of the pointer as an index into the table at CR3 (since there are 2¹⁰ entries), and -- if that PDE is further subdivided (meaning it isn't a "large" page, which you can figure out from the flags) -- you take the top 20 bits of the PDE, look up the page table at that address, and index into it with the virtual address's next-topmost 10 bits. Then the topmost 20 bits refer you to the physical page, assuming the bottom 12 bits tell you the physical page is actually present.

如果您使用物理地址扩展 (PAE)，那么您将获得另一个 层次结构中最顶层的级别.

If you're using Physical Address Extension (PAE), then you get another level in the hierarchy at the very top.

注意:为了您自己的理智(可能还有 CPU)，您可能希望将页面目录和页表 映射到它们自己，否则事情会很快变得混乱.:)

Note: for your own sanity (and maybe the CPU's), you'd probably want to map the page directory and the page table to themselves, otherwise things get confusing fast. :)

TLB 是硬件管理的——因此页表的缓存是透明的——但是有一条指令 InvlPG 会为您使 TLB 中的 PTE 无效.(我不知道什么时候应该使用它，什么时候不应该使用它.)

The TLB is hardware-managed -- so the caching of the page tables is transparent -- but there is an instruction, InvlPG, that invalidates a PTE in the the TLB for you. (I don't know exactly when you should use it and when you shouldn't.)

来源:http://wiki.osdev.org/Paging

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